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System Design and Verification Community
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Recent Blog Posts
Is anybody out there a Software Verification Engineer?
By
Jason Andrews
on July 16, 2008
In my 2004 book, Co-Verification of Hardware and Software for ARM SoC Design, I wrote about the concept of a co-verification engineer. It's the very...
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C-to-Silicon Compiler Launch
By
Ran Avinun
on July 14, 2008
On July 14th, Cadence introduced C-to-Silicon Compiler, a next-generation high-level synthesis product that improves designer productivity up to 10x in ...
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Functional Verification Community
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Trip to SoCal "techtorials" on CDV
By
Joseph Hupcey III
on July 20, 2008
Just finished packing for a quick trip to Southern California to help kickoff a round of "techtorials" on Coverage-Driven Verification (CDV) t...
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The value of chaos (really!)
By
Joseph Hupcey III
on July 13, 2008
Ordinarily chaos is bad thing. Yet like it or not, the world your SoC lives in is in complete chaos -- your chip will see all sorts of unexpe...
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Logic Design Community
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High on Low Power
By
Jack Erickson
on July 12, 2008
Low power design has been a ubiquitous topic in the electronics industry the past couple years. The term "holistic" is often used (or ov...
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Digital Implementation Community
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Who Designed the iPhone?
By
Bob Dwyer
on July 23, 2008
When people ask you what you do for a living, is your reponse as clumsy as mine? "Um, you see, well I uh, work for this company that sells so...
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Statistical Timing Analysis - Has its time arrived?
By
RahulD
on July 21, 2008
At 45nm chip designs, manufacturing and process control becomes increasingly difficult. Conventional static timing analysis (STA) has been a stock analy...
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Custom IC Community
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Hello from the custom design corner of Cadence
By
Steven Lewis
on July 13, 2008
Greetings! My name is Steve Lewis and I'm a product marketing director working in the custom design area within Cadence. I thought I'd...
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So, where is that mixed-signal behavioral model I ordered?
By
Nigel Bleasdale
on July 12, 2008
It has been said many time that SPICE, the analog engineers tool of choice, is virtually the same as it was 20 years ago, while digital engineers have...
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RF Design Community
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Measuring Transistor ft
By
Arthur Schaldenbrand
on July 16, 2008
So let’s consider a practical example of creating test benches and performing measurements, starting with how to characterize a transistor. A coup...
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Inductors On Demand, at least one RF design task can be really automated!
By
Hany El Hak
on July 13, 2008
Inductors, transformers and transmission lines are critical components in any high frequency integrated circuit. Conventional electromagnetic tools used...
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PCB Design Community
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Second Generation PCI Express spreading roots
By
Brad Griffin
on July 22, 2008
According to Jag Bolaria of the Linley Group, the 5 Gbps version of PCI Express has moved beyond PC applications into embedded systems and netwo...
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Did you know? Enriched schematic content available in PDF files from DEHDL (ConceptHDL)!
By
Jerry Grzenia
on July 16, 2008
For years, Concept-SCALD, and ConceptHDL (DEHDL) customers have been using various methods for generating schematic plots into the PDF format. Some have...
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IC Packaging and SiP Design Community
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PakSi-E "ocho" fuels Cadence Package SI solutions
By
Brad Griffin
on July 12, 2008
In case you haven't heard, Allegro Package SI and Cadence SiP SI solutions now work with the latest and greatest version of PakSi-E (Version 8.1) as...
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Lack of design-chain collaboration prevents SiP to go mainstream
By
Juergen Hartung
on July 11, 2008
A few years back, I was considering that the lack of an integrated design solution (tool flow) was the reason that SiP design was an "expert engine...
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Manufacturability Signoff Community
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DFM in Disguise
By
Wilbur Luo
on July 12, 2008
DFM is an overloaded acronym/word. In some design flows, DFM can be found front-and-center and in others, it is just along-for-the-ride. It may be disgu...
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Allow myself...
By
ChrisClee
on July 11, 2008
In the words of Austin Powers, "Allow myself to..." - well you get the idea. I'm Chris, and I am a Senior Product Marketing Manager ...
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Cadence To Repurchase Zero Coupon Zero Yield Senior Convertible Notes Due 2023 Upon the Election ...
Ricoh Adopts Cadence Encounter Platform For Digital IC Design
Ricoh Adopts Cadence Virtuoso Platform For Its Advanced Custom IC Design Flow
Cadence Expands System-Level Offerings with Introduction of C-to-Silicon Compiler
Power Forward Initiative Momentum Continues with Addition of Three Leading Japanese Design Servic...
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