One language can't solve all design and verification problems. Different teams use different languages to take advantage of the unique features each one provides. As a leader of open standards, Cadence is dedicated to providing continuous support for a variety of design and verification languages and implementation standards.
For implementation tools, Cadence supports LEF, DEF, GDSII, SDF, SPEF, and the ECSM library format.
To date, Cadence has donated and made accessible to the industry more than a dozen major proprietary languages, formats, API specifications, and reference implementations, including Verilog, VHDL, SystemC, GDSII, SDF, LEF, DEF, ECSM.
To ensure unified standards for advanced design and verification, and to improve the process of turning specifications into fully implemented standards, Cadence is an active participant in Accellera and IEEE standards committees.
Verilog
Verilog is the incumbent de facto and IEEE standard (IEEE 1364-2001) for RTL design. It has been in widespread use since the 1980's and is supported by all major EDA vendors. It is the basis for most logic synthesis tools and it provides good support for ASIC design and verification of simple and moderately complex chips. The limitations of Verilog became apparent in the late 1990's as the growing complexity of designs mandated better solutions for verification and increased abstraction levels for effective design and modeling. Verilog remains the language of choice for a broad cross-section of today's' designers who are not involved in cutting edge projects or who use it as an implementation language in a Multilanguage design and verification flow.
VHDL
VHDL (IEEE 1076-2000) enjoys a similar position to Verilog in several geographic and industry segments. While its precise semantics and higher level abstraction appeal to some, it has never fully realized its potential largely because of the lack of gate-level support. VHDL will remain the language of choice for many designers due to its capabilities and legacy.
SystemVerilog
SystemVerilog is an evolving solution and candidate IEEE standard (P1800) that expands on base Verilog® language by adding convenience and abstraction extensions for design. It is then further extended with assertions and multiple levels of testbench constructs for verification. SystemVerilog is well suited for designers wishing to take on or contribute more to RTL verification tasks with limited complexity. Most vendors are in the process of coupling an incrementally larger subset to methodology, technology, and verification IP (VIP).
The Open Verification Methodology (OVM) is the first truly open, interoperable, and proven verification methodology. The OVM is an open-source SystemVerilog class library and methodology that defines a framework for reusable verification IP (VIP) and tests. It is 100% IEEE 1800 SystemVerilog and provides building blocks (objects) and a common set of verification-related utilities. The OVM release will be under the Apache 2.0 license, enabling anyone to use OVM libraries for any purpose, including creation of derivative work. The OVM is jointly developed by Cadence and Mentor Graphics to facilitate true SystemVerilog interoperability with a standard library and a proven methodology.
Property Specific Language (PSL)
PSL supports today's popular RTL description languages, Verilog and VHDL, as well as IBM's internal environment description language, and it includes multiple abstraction layers for assertion types ranging from low-level boolean and temporal to higher-level modeling and verification. There is also a working group that is developing an implementation of PSL for use with SystemC®.
SystemC
SystemC is a mature solution and candidate IEEE standard (P1666) that is ideal for transaction level modeling and high performance reference modeling. Although, like SystemVerilog, the original claims were that it was to replace all languages, in practice, it found its home at the system level. It is particularly powerful in a multi-language environment integrated with e for verification and Verilog or SystemVerilog for implementation.
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