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Common Platform Technology Forum

 
Type:
Forum  
Date:
05 Feb 2013  
Location:
Santa Clara Convention Center,
5001 Great America Parkway, Santa Clara, CA 95054
 

Cadence and the Common Platform Alliance (Samsung, IBM, and GLOBALFOUNDRIES) are working together to enable FinFET-based design for the next generation of high-performance devices. Find out how at this year’s Common Platform Technology Forum.

The forum focuses on collaboration for technology delivery, highlighting the rich and broad ecosystem of design enablement and implementation partners through a Partner Pavilion that features leading EDA, IP, library, mask, packaging, and design services companies.

The event will also feature keynotes from industry leaders and presentations from senior members of the partners' management and technical teams. Emphasis will be on leading-edge process R&D invention and the successful commercialization of next-generation products.

Cadence presentation
Topic: “Challenges of 14nm FinFET Design”
Location: Mission City Ballroom
Time: 3:50pm - 4:50pm

Cadence booth
Visit us to learn more about:
  • 14nm FinFET standard cell and IP design using Virtuoso technology
  • 14nm physical implementation (placement, routing, optimization) using EDI System
  • 14nm extraction, timing, and power signoff using QRC Extraction, Encounter Timing System, and Encounter Power System
  • Fast adoption of essential new interfaces using our Verification IP Catalog
  • Design optimization using our complete and integrated Design IP Solutions

Questions About this Event?
Send email to events@cadence.com