Exhibit Dates and Hours
- Tuesday, February 26
- Wednesday, February 27
9:00am – 6:00pm
- Thursday, February 28
9:00am – 5:00pm
Exhibition Centre Nuremberg
Nuremberg, GermanyHow to Get There »
Cadence Technology Demos
Visit us in hall 4, booth #609
to learn more about the Cadence System Development Suite
and to talk to our experts in the system-level area. We will demonstrate:
Virtual System PlatformDemo 1:
Virtual Prototyping of an Advanced Driver Assist System (ADAS)Problem to solve:
Creation of a virtual platform of an automotive system to enable early SW development and validation before the hardware is available on a prototyping system. Description:
The Cadence Virtual System Platform simplifies the creation and support of virtual prototypes with automated modeling and faster hardware/software debugging. It is part of a connected development flow and is used to validate the system hardware/software interfaces as the RTL becomes available.
This demonstration showcases the capabilities and features of the Virtual System Platform for the development of an automotive application – an advanced driver assistant system (ADAS).
Starting with a functional software implementation of necessary algorithms the demo shows the seamless integration of hardware accelerators as SystemC model as required for alternative hardware/software partition of the application.
Cadence Virtual System Platform for the Xilinx Zynq-7000 EPP Virtual Platform and Embedded Software Development Problem to solve:
Leverage the virtual prototype of the Xilinx Zynq-7000 EPP and start with the HW/SW Co-design and verification before spending the implementing effort to map the design on the real Xilinx Zynq device. Description:
The Zynq virtual platform provides a functionally accurate model of the Zynq-7000 EPP processing system. It is used for porting operating systems, writing device drivers and applications. This demonstration illustrates that the virtual platform, running the same software stack as the physical hardware, can be extended to include devices or IP that are instantiated within the programmable logic. It also shows the value of a virtual platform where entire-system operation can be frozen, and every hardware register and memory address inspected for debug and development purposes.
This demonstration shows a Linux Image Processing on the Zynq-7000 EPP Virtual Platform. The HW accelerators (used in the medical image processing algorithm) are implemented in the Virtual Platform using SystemC models to show the extensibility of this Virtual Platform offering and how customers can start developing their SW application on a customized Zynq-7000 EPP design even before the HW team is done with their Programmable Logic design.
Palladium XP Verification Computing PlatformDemo 3:
Early accelerated verification and debugging of Automotive Ethernet IP or systems on Palladium-XP Problem to solve:
Verify Automotive Ethernet-based systems and analyze the Ethernet traffic between the sender and receiver including the exact timing analysis. Inject failures and see how the system incl. drivers and firmware is handling various errors scenarios. Description:
The Verification Computing Platform Palladium provides a comprehensive test environment for Automotive Ethernet applications. Since the HW is simulated at RTL-level the exact timing of various operating modes and verification scenarios can be tested and debugged.
This demonstration illustrates how the Palladium enables Automotive Ethernet Traffic Analysis, HW/SW co-development/debug before the FPGA prototype or real hardware is available for testing.
Test advanced Automotive Ethernet features like Priority Queuing, Traffic Shaping and Audio Video Bridging (AVB).
Use Palladium for Driver development in leveraging the Error Injection Capability and see how your SW driver handles various error conditions. Run long regressions with stimulus generated from test data and also with real-world stimulus.
Connect the Automotive Ethernet design to the real world via Cadence Ethernet SpeedBridges with RTL designs which incorporate ARM CortexTM processors and Cadence Automotive Ethernet IP.
Accelerated software execution by integrating a virtual prototype of ARM Cortex A15 Quad Core CPU Subsystem together with existing peripherals like memories, controllers and interfaces. Problem to solve:
HW/SW Co-design of an embedded system that is comprised of a CPU (ARM architecture) modeled as virtual platform and proven legacy RTL code for the peripherals. Combining the best of both worlds using Cadence Virtual System Platform and Verification Computing Platform in the hybrid execution mode to enable virtual integration testing. Description:
Using virtual platforms to start SW development early is becoming an accepted practice, but what about validation of that software against the hardware as it is designed and not needing to wait for real silicon?
This demo presents an innovative solution to leverage the software performance of a virtual prototype using Cadence Virtual System Platform (VSP) with high performance RTL running on Cadence Verification Computing Platform (VCP). Delivering more flexibility, usability and debug for early software development, integration and validation of complex embedded systems well in advance of actual silicon/hardware availability.
Rapid Prototyping PlatformDemo 5:
Accelerating embedded software development with FPGA-based prototyping Problem to solve:
Early software development and validation of embedded systems Description:
Embedded processors have become a key component in practically electronic system today, from multimedia over mobile to automotive. Developing and validating the embedded software on time, is on the one hand a major challenge, but on the other hand also an opportunity and competitive advantage when done right. FPGA-based prototyping is a proven and widely used methodology for early software development, however not all prototyping systems are created equal!
This demonstration shows how to implement a complete SoC design with embedded processor, embedded graphics core and various interfaces on the Cadence Rapid Prototyping Platform (RPP). We will demonstrate, step-by-step, how a software developer would use such a prototyping system:
- starting with configuring the system, which only takes a few seconds
- booting to a LINUX prompt in less than 2 minutes
- running an application that create visual outputs on a connected monitor
Starting software development early is critical for success in today’s challenging environment, and FPGA-based prototyping gives you a head start by providing a pre-silicon version of the SoC and running it fast enough to enable productive software development and system validation, long before availability of the actual silicon.
Implementing a video subsystem in FPGAs for system validation and test Problem to solve:
Rapid Prototyping to enable functional and visual verification of a video system Description:
A picture says more than a thousand words. This is especially true when it comes to testing and validating graphical subsystem, like the ones now found more and more in automotive applications. Can you imagine looking through pages and pages of waveforms to figure out if somewhere on the picture a pixel is missing or has the wrong color? Virtually impossible you say, and you are correct!
However, traditional verification tools like simulation are not fast enough to generate images and display it on a real monitor - this is where FPGA-based prototyping comes into play. It enables the user to implement a whole video subsystem and run at a high enough performance to see and verify moving pictures.
In this demonstration we implement such a video subsystem in the Cadence Rapid Prototyping Platform (RPP). The video source is a camera sensor, like the ones found in many cars today as part of the rearview monitoring system. The video output is a standard LCD panel, and in between, implemented in RPP, is the video subsystem that captures the sensor data, processes the image and generates the output for the monitor. Such a configuration enables the user to verify and test the whole system, hardware and software, to assure correct functionality and highest quality.
The best of both worlds – FPGA-based prototype + virtual prototype enables early system integration Problem to solve:
Hybrid verification of a system that is described in SystemC and RTL Description:
Starting embedded software development and system integration as early as possible is of critical importance for delivering high-quality products and bringing them to market at the right time. Virtual prototypes as well as FPGA-based prototypes are increasingly deployed to achieve these goals. Both have their own advantages and also challenges, but combing both will give you the best of both worlds and deliver a uniquely powerful environment for early system integration.
This demonstration shows how an embedded system is implemented in a combination of virtual prototype (VSP) and FPGA-based prototype (RPP), connected through a high-performance transaction interface, conforming with the SCE-MI 2.1 industry standard. The processor and image subsystems reside in the virtual platform, while the rest of the system and the physical interfaces are implemented in the FPGA-based prototype. The connection between the two is an AXI bus transactor running over a PCIe link.
Such a configuration allows to connect high-performance, instruction-accurate processor models in the virtual platform to seamlessly connect to the cycle-accurate RTL models in the FPGA-based prototype, providing highest flexibility, usability and performance for early software development and integration of embedded systems.
If you are interested in our PCB and Sigrity solutions, visit our experts in the FlowCad booth # 321, hall 4
or find us at the ARM booth # 336
also in hall 4
Go to www.embedded-world.de/e-gutschein
and enter code: 261520
Schedule a meeting
Send an email to firstname.lastname@example.org
and we’ll connect you with our embedded software experts or arrange a private demo.
Cadence Conference PapersWednesday, February 27Embedded Design Automation 10:00am–10:30am
Utilizing Mixed-Language Virtual Platforms for Programmable SoC FPGA DesignJason Andrews Embedded Design Automation II2:30pm–3:00pm
Hardware/Software Co-Debug and Co-Verification Environment for Embedded SystemsMarkus Winterholer FPGA and ASIC Design / SoC II4:00pm–4:30pm
FPGA-Based Rapid Prototyping: Help or Distraction for Embedded System Development?Juergen Jaeger