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DVCon 2013

 
Type:
Industry Conference  
Date:
25 Feb 2013 - 28 Feb 2013  
Location:
DoubleTree Hotel, San Jose, CA  

DVCon is the premier conference for functional design and verification, bringing you information from the leading edge of technology, techniques, and standards. Visit Cadence in booth #1102 and we’ll introduce you to the latest tools, methodologies, and support you need for designing and verifying complex silicon, SoCs, and systems.
  • Talk to our experts in verification IP and IC/SoC/system-level verification
  • Dine with us on Wednesday and listen to a panel on Best Practices in Verification Planning
  • Join us for a Thursday tutorial on how to Fast Track Your UVM Debug Productivity with Simulation and Acceleration
  • Gain real-world insight from our presenters in the technical sessions
The following sessions feature Cadence presenters and co-authors:

Feb 25: 1:30pm-4:30pm Session 3T Tutorial Low-Power Design, Verification, and Implementation with IEEE 1801 UPF John Biggs - ARM
Sushma Honnavara-Prasad - Broadcom
Dr. Qi Wang - Cadence
Erich Marschner - Mentor Jeffrey Lee - Synopsys
Fir Ballroom
Feb 25: 9:00am-12:00pm Session 2T Increasing Productivity with SystemC in Complex System Design and Verification Stuart Swan - Cadence
Trevor Weiman - Intel
David Black - Doulos
Shabtay Matalon - Mentor Graphics
Jon McDonald - Mentor Graphics
Nithya Ruff - Synopsys
Charu Khosla - Synopsys
Oak Ballroom
Feb 26: 9:00am-10:30am Session 2.1 Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards Joerg Mueller, Cadence Fir Ballroom
Feb 26: 9:00am-10:30am Session 2.3 How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification Engineers James S. Pascoe - STMicro
Steve Hobbs - Cadence
Fir Ballroom
Feb 26: 9:00am-10:30am Session 3.1 How to Kill 4 Birds with 1 Stone—In a Highly Configurable Design Using Formal to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications Saurabh Shrivastava - Xilinx
Kavita Dangi - Xilinx
Darrow Chu - Cadence
Mukesh Sharma - Xilinx
San Jose/Santa Clara Ballroom
Feb 26: 1:00pm-3:00pm Session 4.2 Best Practices in Verification Planning Paul Carzola, Cadence Oak Ballroom
Feb 27: 12 noon-1:15pm Lunch Expert Panel: Best Practices in Verification Planning John Brennan - Product Director Cadence
Jason Sprott - Chief Technology Officer Verilab
Mike Stellfox - Verification Fellow Cadence
Dr. Ambar Sarkar - Chief Verification Technologist Paradigm Works
Neyaz Khan - Distinguished Member of Technical Staff Maxim Integrated
Vigyan Singhal - President and CEO OSKI Technology
Meirav Nitzan - Lead Verification Methodologist Xilinx
Pine/Cedar Ballroom
Feb 27: 3:30pm-4:30pm Panel Industry Leaders Panel: The Road to 1M Design Starts JL Gray, VeriLab with panelists: Yervant Zorian - Synopsys
Ziv Binyamini - Cadence
Sunil Shenoy - Intel
John Costello - Altera
Serge Leef - Mentor
Oak/Fir Ballroom
Feb 28: 8:30am-12 noon Session 5T Fast Track Your UVM Debug Productivity with Simulation and Acceleration Nadav Chazan - Cadence R&D
Devinder Gill - Cadence Product Engineering
Kishore Karnane - Cadence Product Management
Donner Ballroom


Cadence is also presenting in the following poster sessions Tuesday, February 26th 10:30-11:30 Gateway Foyer

1P.2 Can You Even Debug a 200M+ Gate Design?
Speaker: Horace Chan - PMC-Sierra, Inc.
Authors: Brian Vandegriend - PMC-Sierra, Inc.
Deepali Joshi - PMC-Sierra, Inc.
Corey Goss - Cadence Design Systems, Inc.
Horace Chan - PMC-Sierra, Inc.
1P.6 A Reusable, Scalable Formal App for Verifying any Configuration of 3D IC Connectivity
Speaker: Daniel Han - Xilinx, Inc.
Authors: Benjamin Ting - Xilinx, Inc.
Walter Sze - Xilinx, Inc.
Darrow Chu - Cadence Design Systems, Inc.
Daniel Han - Xilinx, Inc.
1P.10 Real Number Modeling: How to Verify Mixed Signal Behavior using Event-Based Simulation
Speaker: Wes Queen - IBM Corp.
Authors: Tom Cole - IBM Corp.
Dan Romaine - Cadence Design Systems, Inc.
Wes Queen - IBM Corp.
Mark Kautzman - IBM Corp.
1P.11 Low-Power Verification Automation – A Practical Approach
Speaker: Shaji K. Kunjumohamed - Broadcom Corp.
Authors: Shaji K. Kunjumohamed - Broadcom Corp.
Hendy Kosasih - Cadence Design Systems, Inc
1P.21 Taming the Beast: A Smart Generation of Design Attributes (Parameters) for Verification Closure using Specman
Speaker: Meirav Nitzan - Xilinx, Inc.
Authors: Meirav Nitzan - Xilinx, Inc.
Yael Kinderman - Cadence Design Systems, Inc.
Efrat Gavish - Cadence Design Systems, Inc.
1P.25 Maximize Vertical Reuse, Building Module to System Verification Environments with UVM e
Speaker: Horace Chan - PMC-Sierra, Inc.
Authors: Horace Chan - PMC-Sierra, Inc.
Brian Vandegriend - PMC-Sierra, Inc.
Deepali Joshi - PMC-Sierra, Inc.
Corey Goss - Cadence Design Systems, Inc.
1P.26 Unconstrained UVM SystemVerilog Performance
Speaker: Wes Queen - IBM Corp.
Authors: Wes Queen - IBM Corp.
Justin A. Sprague - Cadence Design Systems, Inc.
John Pierce - Cadence Design Systems, Inc.

Questions About this Event?
Send email to events@cadence.com