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| 15 May 2013 - 21 May 2013 | Technology on Tour India 2013 Join Cadence at one of our Technology on Tour sessions to learn about the latest solutions addressing the design and verification needs of the global electronics industry. Our experts will share with you the newest products, flows, and methodologies to help you develop advanced silicon, systems-on-chip (SoCs), and systems – faster and more profitably.
Event details » | Bangalore, Hyderabad, Pune | Seminar | System Design and Verification, Functional Verification, Digital Implementation, Custom IC Design, Front-end Closure, Mixed-Signal | | 20 May 2013 | IPC ESTC 2013 - DDR3 Interface Design and Analysis This workshop takes users through the steps required to use the DDR3 design-in kit. Upon completion, users will be able to use the kit on their own DDR3 memory interface designs.
Event details » | The New Tropicana, Las Vegas, NV | Workshop | PCB Design | | 21 May 2013 | Cadence Ethernet Protocol DayThis free half-day seminar is intended for VLSI and Verification Engineers. Cadence technical worldwide experts will describe the protocol principles, and present different scenarios that require special attention when dealing with the implementation and verification of ETHERNET protocol.
Event details » | Hertzelia, Israel | Cadence Event | Functional Verification | | 23 May 2013 | A Completely Validated Solution for Designing to the TSMC 20nm Process Using Cadence ToolsInterested in advanced node designs? Enhance your expertise with two new webinars from TSMC and Cadence. Learn about how in-design design rule checking (DRC) and double patterning technology (DPT) checking can improve productivity; how to efficiently manage coloring data in front-to-back custom design flows; how local interconnect layers are supported within the Cadence Virtuoso platform and TSMC’s 20nm process technology and the Cadence methodology to support this process.
Event details » | On line at 9:00am and 6:30pm PDT | Webinar | Advanced Node | | 19 Jun 2013 | Introducing Low-Power Verification RAK (Rapid Adoption Kit)This webinar walks you through the power format file using the example design provided in the RAK, and outlines the implicit logic inferred from the power intent file. You’ll also see a demo of the latest Cadence low-power verification debug applied to the example, and learn how to download the RAK for your own use.
Event details » | Online | Webinar | Functional Verification, Low-Power | | 26 Jun 2013 | Simplify UVM Debug with Cadence Incisive SimVisionThis webinar walks you through the advantages of using the debug power of the Cadence Incisive SimVision unified graphical debugging environment within a complex, class-based SystemVerilog environment for both interactive and post-process debug. We will showcase some of the new SimVision enhancements that improve overall debug productivity.
Event details » | Online | Webinar | Functional Verification | | 11 Jul 2013 | CDNLive Taiwan 2013CDNLive Taiwan brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.
Event details » | Hsinchu, Taiwan | Cadence Event | All | | 16 Jul 2013 | CDNLive Korea 2013CDNLive Korea brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.
Event details » | Seoul, Korea | Cadence Event | All | | 17 Jul 2013 | Configurable Specman Messaging for Improved ProductivityIn this webinar we will expose previous shortcomings and reflect how the new infrastructure solves those issues.
Event details » | Online | Webinar | Functional Verification | | 19 Jul 2013 | CDNLive Japan 2013CDNLive Japan brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.
Event details » | Pan Pacific Yokohama Bay Hotel , Yokohama, Japan | Cadence Event | All | | 06 Aug 2013 | MemCon 2013MemCon, the memory industry’s premier technical and ecosystem event, showcases the thought leaders driving advances in memory technology. After a successful return in 2012, MemCon will be held August 6, 2013 at the Santa Clara Convention Center. Targeting decision makers and innovators in memory, systems integration, IP development, semiconductor design, and SoC development, MemCon offers insights into advanced technologies and standards and opportunities to network with industry leaders.
Event details » | Santa Clara, CA | Industry Conference | System Design and Verification, Functional Verification | | 07 Aug 2013 | Leveraging SystemVerilog Real Number Nets for Analog Behavioral ModelingJoin this webinar to see how Cadence is leveraging this new functionality to provide behavioral modeling solutions to customers.
Event details » | Online | Webinar | Functional Verification | | 27 Aug 2013 | CDNLive Boston 2013CDNLive Boston brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.
Event details » | Boston, MA | Cadence Event | All | | 04 Sep 2013 | Best Practices in Verification PlanningThis webinar articulates a methodology for verification planning based on actual experience at Freescale Semiconductor. The verification planning process described in this session is streamlined for derivatives and comprehensive enough for new design and verification development. It explains a complete verification flow including verification strategy, planning, change management, and closure.
Event details » | Online | Webinar | Functional Verification | | 10 Sep 2013 | CDNLive Beijing, China 2013CDNLive China brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.
Event details » | Beijing, China | Cadence Event | All | | 12 Sep 2013 | CDNLive Shanghai, China 2013CDNLive China brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.
Event details » | Shanghai, China | Cadence Event | All | | 09 Oct 2013 | CDNLive India 2013CDNLive India brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.
Event details » | Bangalore, India | Cadence Event | All | | 14 Oct 2013 | CDNLive Israel 2013CDNLive Israel brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.
Event details » | Tel Aviv, Israel | Cadence Event | All |
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