Home > About Cadence > Newsroom > Cadence Articles > Cadence Introduces Virtuoso Advanced Node for Design Success at 20nm and Below
From Specs to Signoff, Virtuoso Advanced Node Clears the Path to
20nm Success


Migrating to the 20nm process node and below enables cutting-edge chips and systems with incredible performance, but it also introduces design and manufacturing complexities that can be time consuming and labor intensive. At smaller geometries, engineers must address layout-dependent effects (LDEs), double-patterning requirements, and new routing layers.

To address these challenges and enable customers to complete their cutting-edge designs within critical competitive timeframes, Cadence has introduced Virtuoso® Advanced Node, a new set of custom/analog capabilities for designing at 20nm and below. Leading companies, including STMicroelectronics, have already embraced this new Cadence methodology and are benefiting from greater efficiency and predictability with their 20nm projects.

Virtuoso Advanced Node spans specification through signoff. It provides high-quality automation for custom/analog chip design, helping engineers avoid real-time problems and actually preventing errors early in the design process—before they are created. Key capabilities include:

LDE analysis using incremental layout: engineers can build their physical design and check it as they go. They can use a partially completed layout to analyze LDEs (such as stress and parasitics) at the earliest stage possible. Using detailed testbenches, constraints, and hotspot detection/correction tools, engineers can improve overall verification time by up to 30%.

Double patterning and color-aware layout: using real-time, automated, color-aware, design-rule‒driven layout capabilities, engineers can fully optimize their layout for area (which, at 20nm, means the design is split into two layers). They can also identify, debug, and fix errors as they go.

Local interconnect‒aware wire editing and routing: engineers can address new local interconnect rules, allowing them to create densely packed routes inside complex devices while still maintaining signal integrity among pins.

Virtuoso Advanced Node integrates seamlessly with the Cadence Encounter® RTL-to-GDSII flow, QRC Extraction, and Physical Verification System. The new Virtuoso capabilities also work in concert with the Cadence Integrated Physical Verification System (IPVS), a foundry-qualified signoff technology that eliminates iterations by conducting on-the-fly design-rule and double-patterning checks.

“Designing at 20nm and below brings a host of new challenges and complexities, but we knew it was a move we had to make to help cement our technology leadership and help realize our customers’ cutting-edge designs. The new Virtuoso Advanced Node capabilities made our transition much easier by providing high-quality automation for our custom/analog chips. Virtuoso Advanced Node takes into account the idiosyncrasies of designing at 20nm, and helps our engineers avoid problems in real-time for a much more efficient development cycle.”
Pierre Dautriche
Sr. Director, STMicroelectronics
“Moving to smaller geometries always creates new obstacles, but the move to 20nm and below has been especially challenging for our customers, many of whom are reporting that layout is taking 2 to 5 times as long as for 28nm on the same circuit. Virtuoso Advanced Node enables design teams to optimize their designs for performance, power, and area while reducing or even eliminating tasks that would make 20nm design much more time consuming and labor intensive.”
Dr. Chi-Ping Hsu
Sr. Vice President, Silicon Realization Group, Cadence


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