Cadence and Sigma Designs
Cadence Palladium Technology Helps Sigma Designs Compress Verification Schedule Download Cadence and Sigma Designs Success Story »
Sigma Designs, Inc. develops media processor systems-on-chip (SoCs) for products such as Blu-ray players, IPTV set-top boxes, digital-cable set-top boxes, and network players. These products typically require high-definition MPEG- 4.10 (H.264), SMPTE 421M (VC-1), AVS, WMV9, MPEG-4.2, and MPEG-2 decoding.
Sigma’s secure media processor (SMP) designs, specifically the SMP86XX series of products, each typically have from 4 to 10 million gates containing a substantial mix of both in-house and third-party IP components. Many consumer electronics products now have low-power requirements, so to meet these, Sigma Designs typically incorporates additional features like automatic standby modes, with system wake-up commanded by remote control or LAN activity. One of the trickier requirements to achieve with sleep/standby modes is that DRAM data must be preserved, and wake-up must happen quickly.
For set-top box and consumer electronics OEM customers, quality and reliability are prime concerns, as the costs of dealing with product returns are usually prohibitive. Therefore, thorough and effective verification is a must. What makes verification particularly challenging is having many complex IP components working together, orchestrated by several hundred thousand lines of embedded software. It’s impossible to get the level of confidence needed by just exhaustively verifying portions of the system. When problems are discovered and must be debugged, the heavy interaction between the different blocks makes it a real challenge to trace through the hardware and software to find the root cause. For these reasons, verification is the most time-consuming and resource-intensive phase of development, where typically many thousands of video frames are run through the SoCs.
With conventional simulation techniques, a single standard-definition (SD) video frame takes 15 minutes to run, which is clearly inadequate. To incorporate more advanced verification methods, Sigma engineers have worked extensively with Cadence on two simulation acceleration techniques: signal-based acceleration and transaction-based acceleration (TBA).
With HDL simulations of multi-million gate designs, the execution of every software (machine-code level) instruction creates tens or hundreds of thousands of signals and events that must be updated between the testbench and the design under test (DUT) during each clock cycle. And when a design contains multiple clocks, it’s even worse. To process one video frame requires executing thousands of machine-code instructions, so even a very fast workstation would take 15 minutes or more to simulate.
Simulation has the advantage of being easily connectable to analysis and debug environments, so that when you discover a problem, you can easily trace-back in your simulation, view every signal you want in detail, and identify the root cause. This advantage should not be underrated, as identifying the cause of bugs in complex systems can be extremely challenging. Without the ability to observe the internals of the design and signals within both the design and testbench in such accurate detail, debugging would be nearly impossible.
At the other end of the verification spectrum is in-circuit emulation (ICE). In Sigma’s experience, the Cadence® Palladium® series has very strong and mature ICE capabilities. In terms of speed, the advantage of ICE over HDL simulation is huge—in some cases up to 1000x, enabling Sigma to run software and process almost one video frame per second.
Sigma requires the best of both simulation and in-circuit emulation worlds, and has explored different solutions including various simulation acceleration techniques from Cadence. Using these techniques, the Sigma engineering team starts from a simulation perspective and tries to implement as much of the testbenches and monitors as possible in software. Maximizing the overall performance of the verification environment requires minimizing the fraction of total processing spent in the host workstation, and also reducing the number of times the host workstation needs to synchronize and pass data back and forth. With Cadence signal-based and transaction-based simulation acceleration technology, Sigma Designs can start developing firmware once the appropriate RTL modules are ready. The implementation of the processes of FPGA design, PCB manufacturing, and debug can now be run in parallel, reducing the critical path by several months.
The Verification Process
The Sigma SMP86XX design, consisting of 800k gates (not including memory), was compiled to one of the Cadence Palladium platforms. Software and device drivers were run from the workstation to perform MPEG 2/4 video decoding. The testbench contained about 800 video frames, with monitors attached to accurately track the decoded frames along with any errors and to help debug any behavioral anomalies as they came up.
Overall results exceeded Sigma Designs’ expectations. Each individual SD video frame that originally took 15 minutes to process using HDL simulation could now run in just 2.1 seconds using signalbased simulation acceleration, and in just 1.9 seconds with transaction-based acceleration. In addition, by using in-circuit emulation, the processing time was reduced to about 1.5 seconds per frame. Interestingly, simulation acceleration results approached the theoretical optimum performance of the Palladium system.
With transaction-based acceleration, Sigma Designs has now enabled their firmware developers to have earlier access to system-level validation in a pre-silicon verification environment. Using their debug GUI, firmware developers can now develop and test their code: typically, they’ll download micro-code, single-step though their code, set breakpoints, view memory registers stack, and so on—all with the accuracy of actual hardware in a virtualized environment. For their embedded software development and system verification, the Sigma engineering team is comfortable and efficient using simulation acceleration techniques to compress the verification schedule and to start verification activities earlier in the project lifecycle.
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