Encounter RTL Compiler with Physical Helps Zarlink Quickly Realize an Ultra–Low-Power RF Chip for the Medical Industry
As chips become smaller and more complex, and as concerns over power consumption take center stage, knowledge of physical feasibility is crucial input for design optimization. The uncertainty of physical interconnect timing can cause iterations between logical and physical design that do not converge. As a result, engineers are forced to choose: either meet their schedule or achieve their performance, power, and area requirements.
So that companies can optimize end-product quality and still hit their market windows, Cadence developed Encounter RTL Compiler with Physical
. This product embeds Encounter® Digital Implementation System placement technology inside Encounter RTL Compiler's
logic synthesis. Now, logical and physical design teams can see the same representation of a design, speeding closure on their overall design goals. The end result is a more predictable path to silicon realization that meets the most stringent product requirements.
Zarlink’s Complex, Ultra–Low-Power Challenge
Zarlink offers a family of products that support in-body RF communications for medical devices. Their expertise is in producing high-performance radio telemetry chips and modules in a tiny footprint that require the most advanced power-reduction techniques. Zarlink’s latest product was a complex, ultra–low-power medical RF telemetry chip. Because of the form factor requirements, the floorplan was very restrictive. And to reduce power, Zarlink needed to use power islands with power shutoff. They were also dealing with multiple clock domains and multiple functional modes.
These aggressive power and performance targets created a challenge for Zarlink to close on their timing and power goals in the physical design context. By adopting Encounter RTL Compiler with Physical, the Zarlink logic design team could see the physical feasibility of their chip early on, during synthesis. This allowed them to make early adjustments and ultimately deliver a design to place and route that closed more easily on their design goals.
“Because our chip needed to be small and ultra low-power, we needed real physical interconnect visibility during synthesis to understand the physical feasibility of our logic design decisions,” said Bengt-Erik Embretsen, Manager of EDA Engineering for the Zarlink Medical Products Group. “Encounter RTL Compiler with Physical helped us optimize the logic with physical awareness, resulting in improved results in place and route and a 2x speedup of the design closure phase of our project, which reduced the overall project schedule.”
Encounter RTL Compiler with Physical
Because Encounter RTL Compiler with Physical offers production physical technology built right into synthesis, when the logic design team sees that they have met their goals, there will be no surprises in later on during physical design. And the physical design team receives a design that will close much more predictably and with less effort. This is even true for designs with routing congestion.
Because the location of long wires and congestion are dependent on the actual production placement, a production floorplan is required as input to the process for optimal results. As Encounter RTL Compiler with Physical optimizes the design, it incrementally re-places it so that the physical model is always up-to-date. Ultimately, this legal placement can be handed off as DEF output to seed the physical design process, ensuring that the physical design team sees exactly what the logic design team hands off.
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