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Samsung Slashes Regression Time and Speeds Verification of SoCs Using Incisive Enterprise Simulator
As demand grows for increasingly complex mobile application processors, the Samsung LSI Business group is responding. The application processor design team must continue to evolve its system-on-chip (SoC) verification methodology to keep pace and deliver competitive products in shorter time-to-market windows.

This Samsung team recently launched the high-performance Exynos SoC family, which supports low-power requirements and provides optimal processing power for mobile devices. These chips quickly grew to 150 million gates, which meant longer logic simulation runtimes. At the same time, quality remained paramount and time was of the essence.

Using Cadence® Incisive® solutions, the Samsung design team created a methodology and deployed the associated toolset to meet its aggressive project verification goals. It reduced regression turnaround time from five days to one day for register-transfer level (RTL), and from five days to two days for gate-level simulation (GLS).

Overall, Samsung reduced RTL simulation time from 100 to 4 hours and total SoC regression by 42% to achieve its time-to-market goals.

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