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05/15/13
Broadcom
Vahid Ordoubadian, Director - Mobile Platform Group at Broadcom, describes the use of Cadence Palladium XP to validate a new architecture for a complex mobile SoC for mobile platform devices.
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02/05/13
ARM, Samsung and Cadence
Dipesh Patel, EVP and GM, Physical IP Division at ARM, Ana Hunter, VP of Foundry at Samsung Semiconductor and Chi-Ping Hsu, SVP, R&D at Cadence discuss the collaboration between the three companies to develop the first 14nm, FinFET implementation of the ARM Cortex A7.
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01/24/13
Analog Devices
Rohit Pandharipande, Design Engineer at Analog Devices, details working with Cadence migrating from VMM to the UVM Compliant, Cadence Verification IP (VIP) to verify a Dynamic Memory Controller.
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01/22/13
STMicroelectronics
Abhishek Jain, Technical Manager at STMicroelectronics, talks about working with the Cadence Incisive Verification Solution to deploy a UVM multi-language, low-power verification methodology resulting in earlier and integrated verification.
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01/22/13
Open-Silicon, Inc.
Hear from Shrikrishna Mehetre and Souvik Mazmunder, with Open-Silicon, Inc., as they highlight the use of Cadence Encounter digital RTL-to-signoff products to achieve 2.2 GHz performance on a 28nm ARM Dual-Core Cortex-A9 processor.
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01/22/13
Open-Silicon, Inc.
Kavitha Nagarajan, Lead Engineer — IC Package Design at Open-Silicon, Inc., describes how the company leveraged the Cadence Integrated SPB environment to successfully complete a complex project with a tight deadline.
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12/10/12
imec
Antoine Dejonghe, Green Radio Program Manager at imec, highlights the use of the Cadence CPF-Driven Advanced Low-Power Solution that accelerates the company's next generation 4G wireless designs.
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11/21/12
Executive Insight: Market Trends Driving the Need for Collaboration
Executives from Cadence, ARM, TSMC, and Broadcom discuss how three distinct trends in the electronics industry result in design challenges that can only be met through close collaboration among EDA companies, software partners, foundries, and IP partners.
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09/20/12
Saphyrion
Angelo Consoli, Managing Director at Saphyrion, details how they leverage the Cadence Virtuoso custom/analog flow and design services to develop ASICs High-End ground and space applications.
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09/12/12
Duolog
David Murray, CTO at Duolog, discusses collaborating with Cadence to help customers address SoC integration and verification.
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08/27/12
Methods2Business
Listen to Marleen Boonen and Vladislav Palfi, from Methods2Business, as they describe how they use the Cadence Virtual Platform and Verum's Analytical Software Design solution tool to debug earlier in the design cycle and ultimately design software faster and more efficiently.
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08/02/12
Cadence is Ready for 3D-IC Design
Hear from Samta Bansal, product marketing manager, Cadence, talking about the challenges facing EDA vendors with the commercialization of 3D-ICs, and how Cadence is leading the charge.
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08/02/12
Imperas and Cadence Collaboration
Hear from Larry Lapides, Vice President of Sales at Imperas, and Larry Melling Product Manager - Virtual System Platform at Cadence, as they describe the collaboration and use of the Cadence Virtual System Platform along with Imperas' processor models and verification analysis and profiling tools to address challenges of embedded software development for complex SOCs.
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08/02/12
S3
Dermot Barry, VP — Silicon Business Unit at S3, highlights how they leverage Cadence mixed-signal solutions to help their customers achieve business success through fast time to market and first time right silicon with the optimized power, performance and area.
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07/30/12
imec
Luc Van de hove, President and CEO at imec, details imec's business focus and highlights the collaboration between imec and Cadence.
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07/30/12
X-Fab
Dr. Jens Kosch, CTO at X-Fab, highlights the use of the Cadence Mixed-Signal solution to help mutual customers with their designs.
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07/17/12
IBM
Nancy Pratt, BIST Verification Lead at IBM, details the use of Cadence Verification tools to help streamline and provide more detailed reports, improve planning and increase scheduled adherence.
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07/06/12
NVIDIA
Narendra Konda, Director, HW Engineering at NVIDIA, discusses leveraging Palladium XP and the Rapid Prototyping Platform to integrate complex hardware and software designs.
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07/06/12
Freescale Semiconductor
Wai-Chee Wong, Senior Member of Technical Staff at Freescale Semiconductor, details how Palladium XP helps speed their verification effort by 10,000x over simulation
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07/06/12
Xilinx
David Beal, Zynq 7000 EPP Product Manager at Xilinx, describes how the Cadence Virtual System Platform helps to accelerate product development.
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07/06/12
LeCroy
John Wiedemeier, Product Marketing Manager — Protocol Solutions Group at LeCroy, describes the collaboration with Cadence utilizing PCI Express 3.0 to help mutual customers reduce development risk, improved system interoperability and reduce time to market.
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06/22/12
TSMC
Ashok Mehta, Sr. Manager System Verification/Software Architecture describes how they worked with Cadence to Address System-Level Complexity with the TSMC ESL Reference Flow 12.
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06/22/12
GLOBALFOUNDRIES
Luigi Capodieci, Director of Design for Manufacturing, R&D Fellow at GLOBALFOUNDRIES, discusses how they collaborated with Cadence on pattern-matching technologies to accelerate full-chip DFM signoff.
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06/21/12
AMD
Alex Starr, Hardware Emulation Architect at AMD, highlights the unique capabilities of Palladium XP and in-circuit acceleration.
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06/14/12
Silicon Blue Technologies
Andy Chan, Vice President of Engineering at Silicon Blue Technologies details how they utilize the TSMC-certified Cadence DFM Services along with Cadence technologies to develop consumer mobile applications
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06/04/12
IBM
Lars Liebman, Distinguished Engineer at IBM, highlights the collaboration between IBM and Cadence in solving design challenges at 20nm and 14nm technology nodes.
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03/20/12
Freescale Semiconductor
Anis Jarrar, Principal Design Engineer, at Freescale Semiconductor describes how they utilized the Cadence Low-Power Solution to design and implement the complex Kinetis SoC.
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03/20/12
Lip-Bu Tan Honored as Outstanding CEO with 2012 Singapore Business Award
Cadence President and CEO Lip-Bu Tan received the Singapore Business Award as Outstanding CEO (overseas) at a black tie event in Singapore on March 20, 2012.
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02/09/12
Xilinx
Larry Getman, Vice President Processing Platform Marketing at Xilinx describes working with Cadence and the Virtual System Platform to developed the Zynq-7000, the industry's first virtual platform for system design and software development.
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02/09/12
Xilinx and Cadence
Larry Getman, Vice President Processing Platform Marketing at Xilinx and Michael McNamara, VP and GM System Level Design at Cadence highlight the collaboration between Xilinx and Cadence to develop the Zynq-7000.
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01/18/12
BIOTRONIK
David Genzer, Director of IC Development at BIOTRONIK describes how they leveraged the Cadence digital implementation and signoff flow and CPF-enabled low-power solution to help deliver the most advanced and sophisticated pacemaker product on the market.
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12/15/11
ARM Tech Con 2011 Fireside Chat between ARM and Cadence
Listen to this informal conversation between Simon Segars of ARM and Lip-Bu Tan of Cadence to hear how they think collaboration is evolving and what's necessary for success in the era of "apps-driven" multicore designs and 20nm implementation. Get an executive perspective on how to evaluate innovation opportunities and how to drive effective collaboration to capitalize on those opportunities.
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09/22/11
Global Unichip Corporation (GUC)
Alex Kou, Senior Design Manager at Global Unichip Corporation, highlights how the CPF enabled Cadence Low Power Solution helps them achieve 100+ low power design tape-outs and address their low power design challenges in future technology nodes.
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06/06/11
Getting a Jumpstart on 20nm - Part I
Distinguished panelists discuss the challenges and approaches that need to be considered when designing and implementing at the 20nm node. Moderated by Jim Handy, the panel includes Philippe Magarshack - STMicroelectronics, Ana Hunter - Samsung, Simon Segars - ARM, and Chi-Ping Hsu - Cadence.
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06/06/11
Getting a Jumpstart on 20nm - Part II
Distinguished panelists discuss the challenges and approaches that need to be considered when designing and implementing at the 20nm node. Moderated by Jim Handy, the panel includes Philippe Magarshack - STMicroelectronics, Ana Hunter - Samsung, Simon Segars - ARM, and Chi-Ping Hsu - Cadence.
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05/11/11
Josh Moore
Cadence
Josh Moore, Senior Product Manager for OrCAD, shares how the new OrCAD Capture Marketplace — with online apps — transforms the way PCB designers access information, discover new resources and extend the OrCAD environment.
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05/03/11
System Development Suite — Narendra Konda, Director Hardware Engineering, NVIDIA
Narendra Konda of NVIDIA outlines how the Cadence System Development Suite helps his design team successfully integrate complex hardware and software, quickly develop app-ready systems, and ultimately improve the overall quality of their products.
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05/03/11
System Development Suite — Nimish Modi, Senior Vice President, System and Software Realization Group, Cadence Design Systems
Nimish Modi of Cadence discusses system development trends, customer challenges, and how the Cadence System Development Suite enables concurrent hardware/software design and verification at every stage of the development cycle.
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05/03/11
System Development Suite — Ran Avinun, Marketing Group Director, Cadence Design Systems
Ran Avinun of Cadence discusses software development and system engineering requirements and Cadence solution including the two new platforms: the Rapid Prototyping Platform and the Virtual System Platform to address alternative limitations.
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05/03/11
Virtual System Platform — Sanjay Srivastava, SoC realization, Cadence Design Systems
Sanjay Srivastava of Cadence discusses firmware challenges and requirements as part of IP delivery and how Cadence Virtual System Platform helped his team to solve these challenges in order to deliver a high quality software and hardware IP to a Cadence customer on time.
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03/23/2011
Hear about 3D-IC/TSV Design Methodology from Cadence R&D
Find out what it takes to handle 3D-IC/TSV design challenges
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02/23/2011
Cadence Opens NASDAQ Stock Market
Lip-Bu Tan, Cadence President and Chief Executive Officer and members of the Executive Management Team rang the opening bell at the NASDAQ stock market on Tuesday morning, February 23, 2011.
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02/23/2010
Cadence Opens NASDAQ Stock Market
Lip-Bu Tan, Cadence President and Chief Executive Officer and members of the Executive Management Team rang the opening bell at the NASDAQ stock market on Tuesday morning, February 23 marking our 5th anniversary of being listed on the NASDAQ exchange.
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02/04/11
Global Unichip Corporation (GUC)
Albert Li, Director of Design and Development at Global Unichip Corporation, outlines the benefits of partnering with Cadence for giga-gate/GHz, 28nm design.
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02/01/2011
Silansys Semiconductor
Niall O hEarcain, the CEO of Silansys Semiconductor describes the benefits of partnering with Cadence for advanced RF level and multimillion-gate designs.
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02/01/2010
New Encounter Digital Implementation System enables superior design productivity and quality
Sumbal Rafiq, Director of Engineering at Applied Micro Circuits, describes the success with the Cadence Encounter Digital Implementation System.
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12/07/2009
Cadence Virtuoso Gets Major Upgrade
Steve Lewis, product marking director for the Cadence Virtuoso technology, discusses the latest productivity, capacity and ease-of-use enhancements to the company's flagship custom IC and mixed-signal product suite.
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11/10/2009
A Conversation with John Bruggeman, Cadence Chief Marketing Officer
In this video interview, John Bruggeman talks about his previous marketing experience, his role and responsibilities as the new Cadence CMO, as well as the direction ahead for both Cadence and the EDA industry.
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10/19/2009
Cadence-ARM Collaboration
Steve Glaser, corporate vice president of strategy and planning, discusses the collaboration between Cadence and ARM to create a next-generation SoC design flow that accelerates time to market while lowering the cost of SoC integration and verification. The flow provides mutual customers better methods to optimize SoC integration architectures and IP selection, and provides VIP-based automation to speed both performance and functional verification time.
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10/14/2009
Tom Anderson Discusses the Expanded Mmulticore Support for Key Cadence Products
Tom Anderson, product marketing director for enterprise verification, discusses the expanded multicore support for many key Cadence products. Cadence engineers have created parallel algorithms to ensure design teams using multicore machines can reap significant performance benefits.
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10/05/2009
The Incisive Enterprise Verifier
Sarah Lynne Lundell discusses the new Incisive Enterprise Verifier, which delivers the dual power of formal analysis and simulation engines. Sarah discusses some of the product's unique features—and how they can benefit verification teams deploying them.
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05/18/2009
Cadence and Virtutech Extend Metric-Driven Verification to Virtual System Development
In this video, recorded at CDNLive EMEA 2009, Ran Avinun, Marketing Group Director of System Design and Verification at Cadence, describes the combined offerings of Virtutech Simics and Cadence Incisive software extensions and how it improves quality and project predictability for teams creating and using virtual platforms.
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05/18/2009
Hemant Shah Comments on Cadence Announcement of FPGA-PCB Co-Design Solution
Cadence introduced an innovative FPGA-PCB Co-Design solution at CDNLive EMEA 2009. Hemant Shah, Allegro PCB Products Marketing Director at Cadence, explains what this announcement is about through a very short Q&A session.
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06/19/2008
San Jose Mayor Chuck Reed Honors Cadence Design Systems
San Jose Mayor Chuck Reed honors Cadence on its 20th anniversary by declaring June 19, 2008 Cadence Day.
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06/16/2008
Cadence Corporate Overview
Consumers continue to demand sleeker, faster, thinner, and ever more functional electronic devices. Cadence is proud to lead in providing the innovative software that enables our customers to achieve breakthrough results. Take a look to see more of why we are in the things you can't do without.
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06/1/2008
Cadence among the best in Silicon Valley
Last November, Cadence was included in a list of the 50 Best Places to Work in Silicon Valley by San Jose Magazine. As a result of our placement, on June 1, Cadence was featured on the CBS 5 - KPIX television show, Best Places to Work, along with several other leading Bay Area companies.
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04/28/2008
CDNLive! 2008 EMEA
A successful CDNLive! EMEA recently concluded in Munich, Germany. More than 620 customers representing more than 200 European and international companies attended the event. The event centered on the Cadence product roadmap, EDA techtorials, and Designer Expo, and proved to be a constructive networking platform for discussing the various challenges of electronic design automation. In this podcast we hear customers and guest speakers talking about their experience attending the event and it will give you an excellent view on the EDA industry get-together.
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