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Tait Communications
Business Challenges
  • Shorten library creation process
  • Make it easier and faster to locate parts
  • Maximize library management resource utilization
Cadence Solutions
  • Allegro® Design Workbench
  • Allegro PCB Library Workbench
  • Allegro PCB Editor
Lessons Learned
  • Implement automated library management via a phased approach
  • Synchronize Allegro PCB Library Workbench with an ERP system for timely, accurate parts data
Results
  • 25% faster library creation process
  • 25% more schematic capture productivity
  • 10% more PCB design layout productivity
  • 40% less time spent managing parts libraries
  • 15% reduction in duplicated part library effort
  • 20% improvement in library model accuracy
  • More agile regulatory compliance process
  • Access to more up-to-date, accurate parts data
  • Faster, more efficient process to install software updates across the user base
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Lnk
Challenges
  • Needed robust, reliable IP to support MIPI SLIMbus audio bridge product
Cadence Solution
  • MIPI SLIMbus Manager Controller IP (with customizations including FTDI controller and I2S interfaces)
Lessons Learned
  • Developed own test tool for SLIMbus IP in order to remain independent from any IP vendor
Results
  • More than 50% faster time to market for SLIMbus audio bridge product
  • LnK’s customers can minimize risk when moving to silicon
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Freescale Semiconductor
Business Challenges
  • Improve efficiency of top-level verification of mixed-signal SoCs
  • Tap into expertise of digital and analog engineers for top-level verification
Cadence Solutions
  • Virtuoso Analog Design Environment
  • Virtuoso AMS Designer Simulator
  • SimVision Debug
  • Incisive vManager solution
Lessons Learned
  • To ensure backwards compatibility to the legacy directed-test environment, use compiler directives to constrain random stimulus
  • When using a coverage- or metric-driven approach, simulation throughput is crucial, so it’s important to collect enough metrics
Results
  • Orders-of-magnitude faster top-level verification of mixed-signal SoCs using wreal configurations
  • 2X more verification productivity for digital and analog engineers achieved through rapid simulation launch and re-invoke
  • Better coverage and traceability with Incisive vManager solution
  • Better bug detection using behavior wreal models verified against actual schematics
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Fujitsu
Key Challenges
  • Achieve high performance of computing systems
  • Accelerate verification of high-performance computing systems
  • Better understand module behavior at the system level
Cadence Solution
  • Palladium® XP verification computing platform
Lessons Learned
  • Automatically generate assertions, via module level verification, to find overlooked behaviors
Results
  • Caught 1/3 of system bugs
  • More than 150% faster overall verification process and savings of more than one re-spin
  • At least 300% faster post-silicon bring-up
  • 600% better engineering productivity
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Polycom
Business Challenges
  • Automate PCB design routing for faster time to market
  • Continually enhance quality of PCB designs
  • Identify more detailed design constraints
Cadence Solutions
  • Allegro PCB Router
  • Allegro PCB Designer
  • OrCAD Capture CIS
Lessons Learned
  • Spend more upfront time capturing design intent
  • Have design constraints in place before placing the board
Results
  • 10% faster time to market for boards, with 25% faster PCB design cycle
  • $50K saved annually through greater layout design efficiencies, which eliminates need to hire outside layout staff during busy cycles
  • Ability to perform “what if” analysis, resulting in better quality boards
  • Achieving higher quality avoids the tens of thousands of dollars that could be spent in the event of a respin
  • Better alignment between industrial and mechanical design phases contributes to better product quality
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Cavium
Challenges
  • Address increasing schedule pressures for complex, high-speed evaluation boards
  • Accelerate timing closure process while maintaining high quality of boards
  • Take on more projects with current staffing level
Cadence Solutions
  • Allegro® TimingVision™ environment
  • Allegro PCB Designer
  • Allegro PCB Router (previously known as SPECCTRA®)
Lessons Learned
  • Route DDR4 signals spaced at 5X the line width for better noise/coupling immunity
  • Ensure that differential pairs (static and dynamic phases) are all matched before trying to match lengths for all signals in a byte lane
  • Use application modes within Allegro PCB Designer to further increase tuning efficiency
  • Take advantage of user-redefinable, application-mode-sensitive “funckeys” to further shorten overall tuning proces
Results
  • 4X faster timing closure, without compromise on quality
  • Ability to take on increased volume of PCB designs with existing resources
  • Faster “what-if” analysis with fewer layers for boards for routing DDRx interfaces
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ST Microelectronics
Business Challenge
  • Get automotive semiconductor products to market quickly, while adapting to frequently changing customer specifications
Design Challenge
  • Automate RTL ECOs for pre- and post-mask layouts
Cadence Solution
  • Encounter Conformal ECO Designer
Results
  • 4 months average estimated savings in product development time
  • Significant mask-cost savings per design
  • Up to 30% productivity gain for design engineers
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Ricoh
Business Challenges
  • Accelerate development cycle for multifunction printer ASICs
  • Automate verification management process
Design Challenges
  • Lack of effective solutions to avoid missing test cases
  • Need to minimize time spent capturing verification status before actual problem solving
Cadence Solutions
  • Incisive vManager solution
  • Incisive Enterprise Simulator
  • Metric-driven verification (MDV) methodology
Results
  • vManager solution addresses approximately 22% of the missing or incomplete test case issues
  • 2.5 months saved in data collection and reporting time
  • Ability to start resolving issues earlier in the design cycle
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Silicon Labs
Business Challenge
  • Ramp up the company’s product development capabilities
Design Challenge
  • Create and implement efficient design flow and methodology, supported by single toolset, for development of low-energy MCUs
Cadence Solution
  • Integrated mixed-signal, low-power RTLto-signoff flow based on Cadence Assura, Encounter, Incisive, and Virtuoso platforms
Results
  • Saved several months in development time for design flows
  • 20 months after the start-up of the company, the first 32-bit MCU (EFM32 Gecko) was launched, consuming only a quarter of the energy of competing products
  • Developed new 32-bit MCU in just 4 months, saving up to 8 months of effort due to innovative design methodology and focus on re-usability
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Pegatron
Business Challenges
  • Free up resources to support more project requests
  • Enhance productivity of layout team
Design Challenge
  • Faster routing and tuning process for boards
Cadence Solutions
  • Allegro PCB Designer (Auto Interaction Delay Tune feature)
  • Full Allegro suite of products
  • Full OrCAD suite of products
Results
  • Up to 67% faster routing process
  • 75% reduction in engineering resources required for routing and tuning, freeing engineers to work on new projects
  • Faster tuning time
  • Increased customer satisfaction
  • Decrease in errors due to 300 utilities developed in Allegro PCB Designer
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