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Customer Success 
Latest Success Stories
By Category  
Casio
Design Challenge
Migrate Casio engineers to a new transaction-level modeling (TLM)-driven design methodology based on next-generation high-level synthesis (HLS)
Rearchitect legacy designs to maximize the benefit of new process technologies, while avoiding the effort of developing new RTL manually from scratch

Cadence Solution
R&D partnership with Casio engineers to adopt next-generation HLS technology developed at Cadence for production usage at Casio
Comprehensive design and verification methodologies/flows (specified and developed with Casio engineers) to integrate HLS with the rest of Casio production design flows
 Read Full story»
Silicon Laboratories
Design Challenge
Full-chip verification was much too slow with regard to integrating the analog and digital content at the full chip level
Verification productivity must be improved by allowing users to begin the digital verification effort much sooner in the overall process

Cadence Solution
Cadence Incisive Enterprise Simulator running the Digital Mixed Signal option
Cadence Mixed-Signal Solution allows users to seamlessly connect Real Value Models to the digital content
 Read Full story»
NVIDIA
Design Challenge
Having HDI design capabilities in a constraint-driven PCB design flow
Driving micro vias quickly and accurately
Reducing the number of layers on customers’ boards
Shortening the PCB layout design cycle

Cadence Solution
High-speed constraint-driven HDI flow to shorten the design cycle while adhering to high-speed rules
Mitigate risk, boost performance, and increase efficiency with a set of proven, unified PCB design, layout, editing, and routing technologies
Collaboration with NVIDIA engineers to streamline time to productivity with the enhanced flow
 Read Full story»
Renesas
Design Challenge
Migrate Renesas engineers to a new system-level design methodology based on next-generation high-level synthesis (HLS)
Demonstrate significant productivity improvements in creation and retargeting of RTL designs

Cadence Solution
Two-year R&D partnership with Renesas engineers to adapt HLS technology developed at Cadence for production usage at Renesas
Next-generation Cadence HLS technology tailored and refined for real production based on feedback from Renesas engineers
Comprehensive design and verification methodologies/flows specified by and developed with Renesas engineers in order to integrate HLS with other Renesas production design flows
 Read Full story»
Novafora
Design Challenge
Architect, design, and verify an SoC design with 10s of millions of gates
Rapidly integrate and analyze third-party IP into several new architectures to maximize performance and features
Ability to assess system-level performance and validate critical HW/SW functions before silicon is available

Cadence Solution
Create, prototype and verify a new design in as little as three days
Explore dozens of design alternatives in a short period of time
Find severe bugs early with hardware/software co-verification and validation
 Read Full story»
Tagent
Design Challenge
Fully integrate an RFID tag on a piece of silicon
Ensure that the antenna doesn’t interfere with the chip logic
No onsite CAD support team /limited existing infrastructure
Minimize time to productivity

Cadence Solution
Provide a hosted front-end design environment for creating an AMS/RF ASIC
Collaborate with Tagent to design and implement AMS blocks onto a full chip
Mitigate risk and optimize time to productivity with a proven, unified CAD environment
 Read Full story»
Fujitsu Microelectronics
Design Challenge
Align power design around CPF with accurate simulation
Move to smaller geometries
Reduce design time and improve QoS

Cadence Solution
Integrated, proven design solution leverages success in new applications
Accurate verification of final design improves silicon
 Read Full story»
Renesas
Design Challenge
Process variation causes performance/yield tradeoffs
Implement SSTA without huge memory and processing time requirements

Cadence Solution
Encounter Timing System with SSTA
- Very fast, accurate and does not require large work space
- Tightly integrated with other Encounter capabilities
 Read Full story»
Unisys
Design Challenge
Expose hard-to-find bugs early in the design cycle of the complex ES7000 Real-Time Capacity Server Series
Verify design blocks prior to testbench simulation for faster time-to-market

Cadence Solution
The Cadence Incisive Formal Verifier technology as part an assertion-based verification flow was incorporated into the production design flow complementing Incisive Design Team Simulation and Incisive Palladium Emulation
Design with Verification in mind started with logic design teams early in the project cycle minimizing lengthy tail-end functional iterations
Productivity and product quality were dramatically increased
 Read full story »
Sun Microsystems
Design Challenge
Develop the highest throughput and most eco-responsible processor available
Employ a verification platform that could eliminate costly respins and accelerate project completion

Cadence Solution
Seamlessly integrated simulation, acceleration, and in-circuit emulation into a single verification environment
 Read full story »
 
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