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Customer Success 
Latest Success Stories
By Category  
STMicroelectronics
Business Challenge
  • Achieve faster debug of RTL data cache flow
  • Quickly gain familiarity with new testbench for enhanced productivity
Design Challenges
  • Learn testbench environment and manage debug process independently after support from testbench developer ended
  • Detect and resolve bugs faster and earlier in the process
Cadence Solutions
  • Incisive Debug Analyzer
  • Incisive Specman Elite Testbench
  • Incisive Enterprise Simulator
  • SimVision
Results
  • Saved 2 months of debugging time
  • Enhanced team productivity with easy-to-use debug tool
 Read full story»
Uniquify
Business Challenge
Remain competitive by achieving 100% tapeout success in increasingly short timeframes
Design Challenges
Meet aggressive performance, power, and cost goals
Perform comprehensive physical design space exploration and feasibility analysis early in the design process
Cadence Solutions
Encounter Digital Implementation (EDI) System
QRC Extraction
Results
In combination with Uniquify’s design methodology, Perseus, Cadence has helped Uniquify achieve:
25%-30% faster design closure
Faster time to design, leading to faster time to market
Greater efficiency, translating into lower costs
High levels of quality
 Read Full story»
RivieraWaves
Business Challenge
  • Produce highly differentiated low-power Bluetooth 4.1 IP in aggressive timeframes
Design Challenges
  • Migrate from OVM to UVM for next-generation Bluetooth 4.1 IP design verification
  • Find bugs faster and sooner
  • Effectively manage new, complex IP challenges
  • Meet robustness goals while achieving new levels of efficiency
Cadence Solutions
  • Incisive Enterprise Simulator
    • SimVision
    • Incisive Metric Center
  • Incisive Enterprise Manager
Results
  • Reduced the debug cycle in the overall verification project by 30%
  • Reduced the debug cycle in the overall verification project by 30%
  • Quickly and easily migrated from OVM to UVM environment
  • Achieved faster IP delivery to customers, enabling faster time to market
  • Met efficiency goals
 Read full story»
Siemens Healthcare
Business Challenge
New image-chain platform design demanded the highest levels of quality, reliability, and flexibility, which would require a more effective verification environment
Design Challenges
Existing verification flow hampered productivity
Incomplete language implementation and immature tools
Repeated recodes
Lack of automation and reuse
Cadence Solutions
Incisive Enterprise Specman Elite Testbench
Incisive Enterprise Manager
Customer Support
Results
Increased verification productivity by 30% compared to previous methodology
Delivered reliable platform on time, with no unexpected delays
Achieved flexibility for future expansion
 Read full story»
Texas Instruments
Business Challenges
Deliver the best application processor with optimal performance, power consumption, and thermal conditions
Limit power consumption within two watts
Design Challenges
Provide accurate power estimation based on real use cases
Develop a methodology and a power dashboard, and continually track power updates
Achieve close correlation between an architect’s power estimation and actual silicon measurement
Cadence Solutions
Palladium XP Dynamic Power Analysis
Encounter Power System
Results
Power estimation and actual silicon measurement at 96% accuracy
Detected unexpected power peaks and resolved design to lower power consumption
 Read Full story»
Nufront
Business Challenges
Quickly roll out a third-generation dualcore Cortex-A9 mobile computing chip without sacrificing quality
Enable customers to speed up product launches and win more business
Design Challenges
Design a complex chip with 12M gates
Comply with strict mobile-computing platform requirements
Achieve low levels of power consumption and a high level of performance
Cadence Solutions
Palladium XP Verification Computing Platform
Incisive Enterprise Manager
Palladium XP Dynamic Power Analysis
SpeedBridge rate adapters
Results
Sped up simulation goals by approximately 1,000x
Increased productivity while meeting stringent quality requirements
 Read Full story»
Samsung
Business Challenge
Reduce regression turnaround time (TAT) from five days to one day for register-transfer level (RTL), and from five days to two days for gate-level simulation (GLS)
Design Challenges
The application processor system on chip (SoC) would quickly grow to 150 million gates and beyond
Logic simulation runtime takes longer and consumes more memory with each design generation
Cadence Solutions
Incisive Enterprise Simulator
Incisive SimVision
Incisive Enterprise Manager
Incisive Verification IP (VIP)
Accellera’s Universal Verification Methodology (UVM)
Results
Reduced RTL regression time by 80% and GLS by 60%
Achieved 1.5x speed increase for Standard Delay Format (SDF) GLS and 2.2x speed increase for zero-delay GLS
Reduced long-running RTL simulation time from 100 hours to 4 hours
Reduced number of simulation builds from 315 to 20, saving 96% of disk space and 42% of total regression runtime
 Read Full story»
Faraday
Business Challenge
Consistently provide highly differentiated ASIC, SoC, and IP designs to customers while achieving lower cost and faster time to market
Design Challenges
Automate the functional ECO process (including bug fixes and new feature introductions/deletions)
Minimize the risk of quality issues and schedule slips
Cadence Solution
Encounter Conformal ECO Designer
Results
Achieved faster functional ECO implementation turnaround time by minimizing manual work and timeconsuming iterations
Gained the ability to implement complex ECOs, a task nearly impossible using the traditional manual process
Achieved earlier netlist handoff to customers
Reduced manufacturing costs and accelerated time to market for customers
 Read Full story»
Sharp
Business Challenge
Speed a new CMOS image sensor’s time to market without sacrificing product quality
Design Challenge
Address timing and routability convergence challenges
Cadence Solutions
Encounter RTL-to-GDSII flow
Encounter RTL Compiler
Encounter Conformal Equivalence Checker
Encounter Digital Implementation System
Encounter Test
Results
2x improvement in turnaround time
Higher quality results in timing, area, and productivity
 Read Full story»
Rohde & Schwarz
Business Challenges
Meet stringent device specifications and tight time-to-market goals
Design Challenges
Perform complex simulations required to meet the demanding specifications of highfrequency circuits
Cadence Solutions
Spectre Accelerated Parallel Simulator
Spectre Accelerated Parallel Simulator RF Option
AMS Designer Simulator
UltraSim Full-Chip Simulator
Results
Thoroughly evaluated high-performance IC designs while meeting tight time-to-market schedules
Improved productivity while increasing chances of first-time-right silicon
Gained ability to run analyses at low frequencies that were previously impossible due to excessive simulation times
Captured issues earlier in design cycle, avoiding potential reduced lifetime or destruction of device
 Read Full story»
 
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