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Customer Success 

Latest Success Stories
By Category  
ST Microelectronics
Business Challenge
  • Get automotive semiconductor products to market quickly, while adapting to frequently changing customer specifications
Design Challenge
  • Automate RTL ECOs for pre- and post-mask layouts
Cadence Solution
  • Encounter Conformal ECO Designer
Results
  • 4 months average estimated savings in product development time
  • Significant mask-cost savings per design
  • Up to 30% productivity gain for design engineers
 Read full story»
Ricoh
Business Challenges
  • Accelerate development cycle for multifunction printer ASICs
  • Automate verification management process
Design Challenges
  • Lack of effective solutions to avoid missing test cases
  • Need to minimize time spent capturing verification status before actual problem solving
Cadence Solutions
  • Incisive vManager solution
  • Incisive Enterprise Simulator
  • Metric-driven verification (MDV)methodology
Results
  • vManager solution addresses approximately 22% of the missing or incomplete test case issues
  • 2.5 months saved in data collection and reporting time
  • Ability to start resolving issues earlier in the design cycle
 Read full story»
Silicon Labs
Business Challenge
  • Ramp up the company’s product development capabilities
Design Challenge
  • Create and implement efficient design flow and methodology, supported by single toolset, for development of low-energy MCUs
Cadence Solution
  • Integrated mixed-signal, low-power RTLto-signoff flow based on Cadence Assura, Encounter, Incisive, and Virtuoso platforms
Results
  • Saved several months in development time for design flows
  • 20 months after the start-up of the company, the first 32-bit MCU (EFM32 Gecko) was launched, consuming only a quarter of the energy of competing products
  • Developed new 32-bit MCU in just 4 months, saving up to 8 months of effort due to innovative design methodology and focus on re-usability
 Read full story»
Pegatron
Business Challenges
  • Free up resources to support more project requests
  • Enhance productivity of layout team
Design Challenge
  • Faster routing and tuning process for boards
Cadence Solutions
  • Allegro PCB Designer (Auto Interaction Delay Tune feature)
  • Full Allegro suite of products
  • Full OrCAD suite of products
Results
  • Up to 67% faster routing process
  • 75% reduction in engineering resources required for routing and tuning, freeing engineers to work on new projects
  • Faster tuning time
  • Increased customer satisfaction
  • Decrease in errors due to 300 utilities developed in Allegro PCB Designer
 Read full story»
VIA Telecom
Business Challenge
  • Deliver low-power baseband processors in a highly competitive market
  • Meet customers’ increasingly aggressive product development cycles
Design Challenges
  • Automate manual process for verifying power intent of processor designs
Cadence Solutions
  • Encounter Conformal Low Power
  • Encounter Digital Implementation System
  • Encounter RTL Compiler
  • Incisive Enterprise Simulator
Results
  • 30% faster product development process
  • Ability to take on 25% more projects with same resource level, which translates into new business for the company
  • Ability to achieve first silicon success
 Read full story»
Faraday Technology
Business Challenge
  • Produce prototype of highly complex, 300-million-gate SoC—the 1st such effort in Taiwan—in 7 months
  • Grow business through ability to develop large-scale chip designs
Design Challenges
  • Shorten verification and analyses processes
  • Process large database for huge SoC design
  • Manage and integrate different technologies across industries
Cadence Solutions
  • First Encounter® Design Exploration and Prototyping
  • Encounter® Digital Implementation System
  • Encounter Conformal® Equivalence Checker
  • Incisive® verification platform
  • Sigrity™ packaging and PCB signal and power analysis solutions
  • Verification IP Catalog
Results
  • Completed complex design from data-in to tapeout within 7 months
  • Reduced one iteration for timing optimization, extraction, analysis and verification of physical design down to 4 days
  • Expanded design capacity by 10X
 Read full story»
Texas Instruments
Business Challenge
  • Fast time to market and stringent quality and budget goals for SoC designs and foundation IP
Design Challenges
  • Speed turnaround time for simulation and characterization of compiler memories
  • Achieve desired level of results accuracy
Cadence Solutions
  • Virtuoso Foundation IP Characterization
  • Virtuoso Liberate MX
  • Spectre XPS
  • Spectre APS
Results
  • Achieved full SRAM simulation for today’s SoC timing and leakage and static power requirements
  • Achieved a 2X reduction in characterization cycle time compared to previous solution
  • Met quality-of-results goals
 Read full story»
STMicroelectronics
Business Challenge
  • Speed the time to market for developing SoCs incorporating STxP70 extensible processor
Design Challenge
  • Simplify and accelerate the integration of STxP70 extensible processor and extensions into SoC-based designs
Cadence Solutions
  • Cadence Incisive Formal Verifier
  • SoC Connectivity verification application (customized by STMicroelectronics for STxP70 core plus extensions)
Results
  • Easy-to-use, high-performance solution, even for formal verification novices
  • Exhaustive connectivity checks completed in 15-30 minutes, compared with 3-4 days for non-exhaustive checks previously
  • Found connectivity issues 1-2 months earlier than previous methods
 Read full story»
Melexis
Business Challenge
  • Accelerate design process
  • Increase design productivity
  • Lower design costs
Design Challenges
  • Streamline design and verification process
  • Find and fix bugs faster
  • Achieve higher level of design abstraction
Cadence Solutions
  • Cadence Incisive Enterprise Simulator
  • Cadence Incisive Software Extensions
  • Cadence SimVision Debug
  • Cadence Virtuoso Analog Design Environment
Results
  • 15% reduction in IC development time
  • 200X faster simulation via transaction-level model
  • Earlier detection/resolution of bugs
  • Enhanced collaboration between analog and software teams
 Read full story»
IN2P3
Business Challenge
  • Enhance ability to meet aggressive deadlines for particle physics research projects
Design Challenges
  • Automate aspects of FPGA board design,including pin placement and routing schemes
  • Quickly select the optimal FPGA package and pin count for the design
  • Quickly determine the right FPGA configuration and component setup for the design
Cadence Solutions
  • Allegro FPGA System Planner
  • Allegro Design Authoring
  • Allegro PCB Designer
  • Allegro PCB SI
Results
  • Saved one to two months based on FPGA interconnect density on manual FPGA design-in effort for initial design
  • Made late changes to the design easily and in hours vs. weeks
  • Reduced design iterations and, as a result, costs
  • Saved one month of project time due to co-design development ability
 Read full story»
 
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