The Road to Better Software Verification
By Jason Andrews
on August 28, 2008
It seems the debate over the benefits of better software verification is still alive and well. I just read a blog post by Frank Schirrmeister on Software Developer Attitude and the topic of hardware vs. software methodology. Part of the post brings up...
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Filed under: System Design and Verification, Frank Schirrmeister, Intel, Specman
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ESL: The state of the industry and what’s next?
By Ran Avinun
on August 25, 2008
While ESL continues to remain in its infancy, there are signs within the industry pointing towards eventual mainstream usage. With the rapid migration towards advanced process nodes (high capacity), increased hardware and software complexity, and the...
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Filed under: System Design and Verification, advanced process nodes, ESL, ASIC/ASSP
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Embedded Systems Conference Boston 2008
By Jason Andrews
on August 21, 2008
Friday is that last day to get the Early Bird price for the Embedded Systems Conference scheduled for October 28-30 at the Hynes Convention Center in Boston. There are a lot of great sessions on embedded software development including a track on Debugging...
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Filed under: System Design and Verification, Coverage Driven Verification for Embedded Software, Embedded Systems Conference 2008, Jason Andrews, debugging, verification
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iPhone 3G issues - result of HW/SW-co-verification?
By Ran Avinun
on August 19, 2008
In a recent article at cnet, financial analyst said he believes Apple's iPhone 3G reception issues may be the result of some faulty chips. Richard Windsor of Nomura published a research note singling out the iPhone 3G's chipset, made by Infineon...
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Filed under: System Design and Verification, Nomura, Infineon 3G chipset, iPhone 3G, Infineon, Richard Windsor
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ESL gets a new taker
By Ran Avinun
on August 19, 2008
Interesting High-Level Synthesis review by Bryon Moyer at IC Design and Verification Journal. If you want to hear more about High-Level Synthesis and see a live demo, sign-up for a system-level design techtorial at CDNLive! Silicon Valley 2008 on Sept...
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Filed under: CDNLive! Silicon Valley 2008, High-Level Synthesis, IC Design and Verification
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Is Concurrent Engineering actually getting worse?
By Jason Andrews
on August 14, 2008
Today I'm taking a few minutes to jot down a few recent observations about the state of concurrent engineering as it relates to hardware and software verification. Everybody knows that the opportunity exists to improve time-to-market if projects can...
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Filed under: System Design and Verification, ISX, Concurrent Engineering
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Design space exploration
By Ran Avinun
on August 4, 2008
In his latest blog post Space Exploration ... design is , Grant Martin said that ESL synthesis is an important tool in the overall design flow. Grant also mentioned that this capability opens new opportunities for the development of design space exploration...
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Filed under: System Design and Verification, high-level synthesis adoption, C-to-Silicon Compiler
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Transaction-Based Acceleration - Second generation
By Ran Avinun
on July 28, 2008
Transaction-Based Acceleration is becoming more and more important as an extension to In-Circuit Emulation and migration path from simulation. It helps to provide performance gain while maintaining the flexibility of simulation-based tools. There are...
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Filed under: System Design and Verification
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Is anybody out there a Software Verification Engineer?
By Jason Andrews
on July 16, 2008
In my 2004 book, Co-Verification of Hardware and Software for ARM SoC Design , I wrote about the concept of a co-verification engineer. It's the very last section of the book. Although a lot of people told me they read the book (and some actually...
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Filed under: System Design and Verification, EDA, co-verification engineer
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C-to-Silicon Compiler Launch
By Ran Avinun
on July 14, 2008
On July 14th, Cadence introduced C-to-Silicon Compiler, a next-generation high-level synthesis product that improves designer productivity up to 10x in creating and re-using system-on-chip IP. C-to-Silicon Compiler enables engineers to design at a higher...
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Filed under: high-level synthesis adoption, C-to-Silicon Compiler
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