Home > Community > PCB Design

	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

How do you work with hierarchical designs from a front-end design and Constraint Manager entry perspective?
Use ASA/SCM alone and/or in combination with DEHDL
Use DEHDL with dynamic block changes
Use DEHDL with fixed blocks (no dynamic block changes).
Don't use hierarchical design - use flat schematics

	Rambus works with partners on new technologies
	Electronics Weekly

	ChipInvest readying first product for production
	EE Times Europe

	"Chips-in-a-SiP" are a circuit simulation headache
	Chip Design Magazine

Email
Social Web

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

PCB Design Community

Blog
Forum
Resources

	What's good about memristors? Who is planning on using them? By Gerald "Jerry" Grzenia on August 28, 2008 I recently read an interesting article in the August 18, 2008 Electronic Engineering Times magazine titled - " Will memristors prove irresistible?" My brother-in-law who used to work for HP years ago, called me excitedly one evening telling... Read more » Comments (0) Filed under: PCB design, Electronic Engineering Times, memristors

	Techtorials, Demos, Roadmaps ... Poker? By Gerald "Jerry" Grzenia on August 20, 2008 What do these 4 have in common? CDNLive! 2008 San Jose - September 8 - 11, 2008. This is an outstanding event where we can learn about how companies are using Cadence solutions to expand their design environments. While most customers attend this event... Read more » Comments (0) Filed under: Front-end PCB design, AMS simulation, PCB Layout and routing, PCB Signal and power integrity, Library and design data management, PCB design, SPB, Design Entry HDL, Allegro System Architect (ASA), Differential Pair Support, ASA, ConceptHDL, DEHDL, Capture CIS, SPB16.01, Allegro PCB Editor, OrCAD Capture, OrCAD PCB Editor, High-Density Interconnect, HDI, CDNLive

	SPB 16.2 release - Constraint Driven HDI PCB Design Flow By Hemant Shah on August 18, 2008 Today's SPB 16.2 release is significant for the Cadence Allegro and OrCAD families of products, but more importantly, I think it brings a lot of new functionality for PCB designers. I will be talking about the improvements in this release over a few... Read more » Comments (0) Filed under: PCB Layout and routing, PCB design, Allegro PCB Editor, OrCAD PCB Editor, High-Density Interconnect, NVIDIA, Harris, HDI

View older posts »

Visit the PCB Design and PCB SKILL Forum »

There are 37 guest(s) and 0 member(s) online:

Most Active Users

Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

Share

Subscribe

Contact Us

PCB Design Community