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IC Packaging and SiP Community

 
Analog/RF chip designers don't care about the Package?
 By Keith Felton on August 25, 2008
So I have an observation that I would your thoughts/input on. On several occassions I have heard from our sales and AE force that in general, chip designers (layout or circuit designers) generally do not care about the IC Package their work-of-art will... Read more »
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How stable is your IC Package's PDN?
 By Brad Griffin on August 21, 2008
There are three goals for a power a delivery network (PDN): sufficiency, efficiency, and stability. Simultaneous switching of Gigahertz speed signals (i.e. DDR3) has made the stability of power a pressing issue in today’s designs. The Cadence SPB... Read more »
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Breaking down the 'virtual' wall
 By Keith Felton on August 20, 2008
In the last 3-4 months I have seen, and been involved in, a flurry of discussions around driving design using manufacturing assembly data. Call it "IP" if you want -- its fashionable!! At least two world-leading assembly and test companies ... Read more »
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