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Products A - Z
Cadence delivers application specific kits and new-generation platforms of integrated design technologies and methodologies that help you address all aspects of electronics design in the nanometer era.
3
3D Design Viewer
A
Allegro AMS Simulator
Allegro Design Authoring
Allegro Design Entry Capture / Capture CIS
Allegro Design Publisher
Allegro Design Workbench
Allegro FPGA System Planner
Allegro Package Designer
Allegro Package SI
Allegro PCB Designer
Allegro PCB Librarian
Allegro PCB SI
Allegro System Architect
AMS Methodology Kit
Assura Physical Verification
C
Cadence 3D Design Viewer
Cadence ActiveParts Portal
Cadence AMS Methodology Kit
Cadence Chip Optimizer
Cadence Chip Planning System
Cadence CMP Predictor
Cadence Incisive Verification Kit
Cadence InCyte Chip Estimator
Cadence Litho Electrical Analyzer
Cadence Litho Physical Analyzer
Cadence Low-Power Methodology Kit
Cadence MaskCompose Reticle and Wafer Synthesis Suite
Cadence OrCAD Capture / Capture CIS
Cadence OrCAD FPGA System Planner
Cadence OrCAD PCB Designer
Cadence OrCAD Signal Explorer
Cadence Palladium Dynamic Power Analysis
Cadence Palladium series
Cadence Palladium XP Verification Computing Platform
Cadence Physical Verification System
Cadence PSpice A/D and Advanced Analysis
Cadence QRC Extraction
Cadence QuickView Layout and Manufacturing Data Viewer
Cadence RF Design Methodology Kit
Cadence RF SiP Methodology Kit
Cadence SimVision Debug
Cadence SiP Co-Design
Cadence SiP Digital Architect
Cadence SiP Digital Layout
Cadence SiP Digital SI
Cadence SiP Layout
Cadence Space-Based Router
Cadence SpeedBridge Adapters
Cadence VIP Catalog
Chip Optimizer
Chip Planning System
CMP Predictor
C-to-Silicon Compiler
D
Design IP
E
Encounter Conformal Constraint Designer
Encounter Conformal ECO Designer
Encounter Conformal Equivalence Checker
Encounter Conformal Low Power
Encounter DFT Architect
Encounter Diagnostics
Encounter Digital Implementation System
Encounter Library Characterizer
Encounter Power System
Encounter RTL Compiler
Encounter RTL Compiler Advanced Physical Option
Encounter Timing System
Encounter True-Time ATPG
F
First Encounter Design Exploration and Prototyping
I
Incisive Debug Analyzer
Incisive Design Team Manager
Incisive Design Team Simulator
Incisive Desktop Manager
Incisive Enterprise Manager
Incisive Enterprise Simulator
Incisive Enterprise Specman Elite Testbench
Incisive Enterprise Verifier
Incisive Formal Verifier
Incisive Plan-to-Closure Methodology
Incisive Software Extensions
Incisive Verification Kit
Incisive Xtreme series
InCyte Chip Estimator
L
Litho Electrical Analyzer
Litho Physical Analyzer
Low-Power Methodology Kit
M
MaskCompose Reticle and Wafer Synthesis Suite
N
NanoRoute Router
O
Open Verification Methodology
OrCAD Capture and Capture CIS
OrCAD PCB Designer
OrCAD Signal Explorer
P
Physical Verification System
PSpice A/D and Advanced Analysis
Q
QRC Extraction
QuickCycles Service
QuickView Layout and Manufacturing Data Viewer
R
Rapid Prototyping Platform
RF Design Methodology Kit
RF SiP Methodology Kit
S
Sigrity BroadBand Spice
Sigrity OptimizePI
Sigrity OrbitIO
Sigrity PowerDC
Sigrity PowerSI
Sigrity Speed2000
Sigrity SystemSI
Sigrity Transistor-to-behavioral Model Conversion (T2B)
Sigrity Unified Package Designer (UPD)
Sigrity XcitePI
Sigrity XtractIM
SiP Digital Architect
SiP Digital Layout
SiP Digital SI
SiP Layout
SoC Encounter RTL-to-GDSII System
Space-Based Router
SpeedBridge Adapters
V
Virtual System Platform
Virtual System Platform for the Xilinx Zynq-7000 EPP
Virtuoso Accelerated Parallel Simulator
Virtuoso AMS Designer
Virtuoso Analog Design Environment
Virtuoso Chip Assembly Router
Virtuoso DFM
Virtuoso Digital Implementation
Virtuoso Layout Migrate
Virtuoso Layout Suite
Virtuoso Liberate
Virtuoso Liberate LV
Virtuoso Liberate MX
Virtuoso Multi-Mode Simulation
Virtuoso Passive Component Designer
Virtuoso Power System
Virtuoso RF Designer
Virtuoso Schematic Editor
Virtuoso SiP Architect
Virtuoso Spectre Circuit Simulator
Virtuoso UltraSim Full-Chip Simulator
Virtuoso Variety
Virtuoso Visualization and Analysis
VoltageStorm Power Verification
Content Query Web Part [1]
New White Paper: 3D ICs With TSVs — Design Challenges and Requirements
Cadence Offers Optimized Implementation Methodology for Silicon Realization of New ARM Cortex-A15 MPCore Processor
Cadence Drives Giga-Gate/Gigahertz Design at 28nm with New Digital End-to End Flow
Content Editor Web Part [3]
Design Communities
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Functional Verification
Logic Design
Digital Implemntation
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RF Design
PCB Design
IC Packaging and SiP Design
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Content Query Web Part [2]
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