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Custom IC Design
Circuit design
Selectively automating non-critical aspects of custom IC design allows engineers to focus on precision-crafting their designs. Cadence® circuit design solutions enable fast and accurate entry of design concepts—which includes managing design intent in a way that flows naturally in the schematic—coupled with an advanced design environment that allows designers to visualize and understand the many interdependencies of an analog, RF, or mixed-signal design and their effects on circuit performance.
Virtuoso Schematic Editor
Fast and flexible design entry, including well-defined component libraries
Learn more
»
Virtuoso Analog Design Environment
The industry standard for fast and accurate design verification for custom ICs
Learn more
»
Cadence AMS Methodology Kit
Handles complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs functional checks to verify clock synchronization.
Learn more
»
Block-level simulation
Dealing with smaller blocks—where the emphasis is on accuracy vs. speed—requires block-level simulation. As part of an integrated solution that meets the changing simulation needs of designers—from architecture exploration to block-level development to RF design and to final full-chip verification—Cadence® block-level simulation technology automates the testbench function to quickly show the designer that the circuit is working correctly.
Virtuoso Multi-Mode Simulation
Comprehensive design and verification delivered by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle
Learn more
»
Virtuoso Spectre Circuit Simulator
Fast, accurate SPICE-level simulation for even the most technically challenging analog and mixed-signal circuits
Learn more
»
Virtuoso Accelerated Parallel Simulator
Provides the next generation SPICE accurate simulation, with scalable performance and capacity
Learn more
»
Cadence AMS Methodology Kit
Handles complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs functional checks to verify clock synchronization.
Learn more
»
Chip-level simulation
Chip-level simulation looks at all the blocks in a design as a whole and concentrates on performance vs. accuracy. Cadence® chip-level simulation solutions provide the large capacity plus high performance required to give assurance that a full chip is working as intended, irrespective of how the blocks perform in aggregate.
Virtuoso Multi-Mode Simulation
Comprehensive design and verification delivered by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle
Learn more
»
Virtuoso Spectre Circuit Simulator
Fast, accurate SPICE-level simulation for even the most technically challenging analog and mixed-signal circuits
Learn more
»
Virtuoso Accelerated Parallel Simulator
Provides the next generation SPICE accurate simulation, with scalable performance and capacity
Learn more
»
Virtuoso UltraSim Full-Chip Simulator
Capacity, accuracy and speed for transistor-level verification of large custom digital, analog/mixed-signal, RF, memory, and SoC designs
Learn more
»
Cadence AMS Methodology Kit
Handles complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs functional checks to verify clock synchronization.
Learn more
»
Mixed-signal simulation
Today’s system-on-chip designs combine complex analog and digital blocks, requiring thorough testing and analysis of how analog and digital circuits interact and the influence they have on each other. Cadence® mixed-signal simulation solutions blend output results from industry-leading block-level and full-chip analog simulators with output from advanced digital analysis technologies. This superior approach to analysis also includes an extensive multi-language capability and the ability to add in RF information.
Virtuoso Multi-Mode Simulation
Comprehensive design and verification delivered by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle
Learn more
»
Virtuoso Accelerated Parallel Simulator
Provides the next generation SPICE accurate simulation, with scalable performance and capacity
Learn more
»
Virtuoso AMS Designer
Flexible mixed-signal verification that links advanced Virtuoso and Incisive technologies
Learn more
»
Cadence AMS Methodology Kit
Handles complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs functional checks to verify clock synchronization.
Learn more
»
Physical implementation
Physical implementation involves taking the concept captured in the schematic and transforming it into a digital blueprint that represents how the chip will actually be manufactured. The Cadence® correct-by-construction physical implementation solution draws on design rules from the foundry as well as the custom designer’s own experience, enabling the software to perform place-and-route in a “custom” way.
Virtuoso Layout Suite
Rapid physical layout, including automation to accelerate block authoring and simplify enforcement of advanced node process and design rules
Learn more
»
Cadence AMS Methodology Kit
Handles complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs functional checks to verify clock synchronization.
Learn more
»
Routing
Once all the devices in a design have been “placed down” they must then be “connected up” with routing, and custom IC designers typically hand-route the critical nets to limit the influence of parasitics. Cadence® routing solutions take the hand-route decision made by the designer and automate the process of routing the remaining nets based on design rules—which, at the smaller nodes, become too numerous to reference manually.
Virtuoso Layout Suite
Rapid physical layout, including automation to accelerate block authoring and simplify enforcement of advanced node process and design rules
Learn more
»
Virtuoso Chip Assembly Router
Automated and interactive block and chip authoring for custom digital, mixed- signal, and analog designs—at any level of the hierarchy
Learn more
»
Cadence Space-Based Router
Performance, capacity and features to handle designs with growing complexity and increasing digital and analog/mixed-signal content
Learn more
»
Cadence AMS Methodology Kit
Handles complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs functional checks to verify clock synchronization.
Learn more
»
Parasitic extraction and analysis
After routing, designers must go back into the design to find the parasitics, and then perform another round of simulation to analyze where parasitic effects will cause problems. Cadence® solutions for parasitic extraction and analysis make it easy to get a holistic view of all the parasitic effects in a design, and then correct them as soon as possible by flagging violations of design rules in real time.
Virtuoso Analog Design Environment
The industry standard for fast and accurate design verification for custom ICs
Learn more
»
Cadence QRC Extraction
Extracts and analyzes full-chip parasitics quickly and accurately. Accelerates timing closure and delivers higher quality of silicon.
Learn more
»
Cadence AMS Methodology Kit
Handles complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs functional checks to verify clock synchronization.
Learn more
»
Chip finishing
The final stage of creating a custom IC involves merging analog and digital elements by performing the top-most routing and power routing (power lines and clock trees). The unique Cadence® approach to chip finishing brings to bear many of the best Encounter® digital IC and Virtuoso® custom IC design technologies in a virtually seamless solution that delivers more accurate full-chip implementation.
SoC Encounter RTL-to-GDSII System
Combines RTL synthesis, silicon virtual prototyping, automated floorplan synthesis, clock network synthesis, design for manufacturability and yield, low-power and mixed-signal design support, and nanometer routing. Allows engineers to synthesize to a flat virtual prototype implementation at the beginning of the design cycle.
Learn more
»
Cadence AMS Methodology Kit
Handles complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs functional checks to verify clock synchronization.
Learn more
»
Manufacturability signoff
At today’s advanced nodes, custom IC design software must account for challenges of smaller transistors and wires, as well as the data capacity and complexity challenges of denser and more complex chips. Cadence® solutions for manufacturability take the knowledge of creating the mask and how the chip is going to be manufactured and bring it back into the design phase. This helps designers compensate for physical effects at nanometer geometries while providing a reliable way to achieve manufacturing signoff before tapeout.
Assura Physical Verification
Performs design rule checking and layout vs. schematic verification to deliver high-yielding custom IP for SoC designs.
Learn more
»
Cadence Physical Verification System
Offers a front-to-back design, implementation, and signoff flow in a single solution. Speeds turnaround of design rule check and layout versus schematic verification.
Learn more
»
Cadence Chip Optimizer
Uses a 3D space-based approach that models, analyzes, and optimizes layout based on electrical constraints, manufacturing rules, and objectives.
Learn more
»
Cadence CMP Predictor
Optimizes design performance through model-based intelligent metal fill and hotspot detection and correction.
Learn more
»
Cadence AMS Methodology Kit
Handles complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs functional checks to verify clock synchronization.
Learn more
»
Library development
As the geometries in newer technologies continue to shrink, developing libraries of cells matched to a particular manufacturing process becomes increasingly important. Cadence® library development solutions not only automate cell development, library validation, and creation of the component technologies, but also facilitate IP reuse.
Virtuoso Layout Migrate
Rapid physical layout migration, including support for complex design rules at advanced nodes
Learn more
»
Cadence AMS Methodology Kit
Handles complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs functional checks to verify clock synchronization.
Learn more
»
Assura Physical Verification
Performs design rule checking and layout vs. schematic verification to deliver high-yielding custom IP for SoC designs.
Learn more
»
Cadence AMS Methodology Kit
Handles complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs functional checks to verify clock synchronization.
Learn more
»
Cadence Chip Optimizer
Uses a 3D space-based approach that models, analyzes, and optimizes layout based on electrical constraints, manufacturing rules, and objectives.
Learn more
»
Cadence CMP Predictor
Optimizes design performance through model-based intelligent metal fill and hotspot detection and correction.
Learn more
»
Cadence Physical Verification System
Offers a front-to-back design, implementation, and signoff flow in a single solution. Speeds turnaround of design rule check and layout versus schematic verification.
Learn more
»
Cadence QRC Extraction
Extracts and analyzes full-chip parasitics quickly and accurately. Accelerates timing closure and delivers higher quality of silicon.
Learn more
»
Cadence Space-Based Router
Performance, capacity and features to handle designs with growing complexity and increasing digital and analog/mixed-signal content
Learn more
»
SoC Encounter RTL-to-GDSII System
Combines RTL synthesis, silicon virtual prototyping, automated floorplan synthesis, clock network synthesis, design for manufacturability and yield, low-power and mixed-signal design support, and nanometer routing. Allows engineers to synthesize to a flat virtual prototype implementation at the beginning of the design cycle.
Learn more
»
Virtuoso Accelerated Parallel Simulator
Provides the next generation SPICE accurate simulation, with scalable performance and capacity
Learn more
»
Virtuoso AMS Designer
Flexible mixed-signal verification that links advanced Virtuoso and Incisive technologies
Learn more
»
Virtuoso Analog Design Environment
The industry standard for fast and accurate design verification for custom ICs
Learn more
»
Virtuoso Chip Assembly Router
Automated and interactive block and chip authoring for custom digital, mixed- signal, and analog designs—at any level of the hierarchy
Learn more
»
Virtuoso Layout Migrate
Rapid physical layout migration, including support for complex design rules at advanced nodes
Learn more
»
Virtuoso Layout Suite
Rapid physical layout, including automation to accelerate block authoring and simplify enforcement of advanced node process and design rules
Learn more
»
Virtuoso Multi-Mode Simulation
Comprehensive design and verification delivered by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle
Learn more
»
Virtuoso Schematic Editor
Fast and flexible design entry, including well-defined component libraries
Learn more
»
Virtuoso Spectre Circuit Simulator
Fast, accurate SPICE-level simulation for even the most technically challenging analog and mixed-signal circuits
Learn more
»
Virtuoso UltraSim Full-Chip Simulator
Capacity, accuracy and speed for transistor-level verification of large custom digital, analog/mixed-signal, RF, memory, and SoC designs
Learn more
»
Content Query Web Part [2]
New Multi-Mode Simulation Technologies Dramatically Boost Speed and Capacity
Cadence Strengthens Solutions for Advanced Node Design with New, Production-Proven Custom IC Technologies
Virtuoso Multi-Mode Simulation, a Complete Solution for Custom IC Designs White Paper
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Content Query Web Part [3]
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