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Functional Verification 

Metric-driven verification
Metric-driven verification (MDV) ensures verification project predictability, productivity, and quality. It uses specifications to create verification plans capturing verification intent, performs metrics analysis/reporting, measures progress, and automates verification tasks. MDV enables coherent verification by driving convergence across digital, analog, and low-power domains among IP and SoC teams to ensure high quality at every milestone, from systems to silicon. MDV uses the test suites and verification plans provided with the Cadence Verification IP products to simplify adoption.
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Functional safety solution
Our comprehensive functional safety solution accelerates what can otherwise be a time-consuming process of complying with functional safety requirements by automating fault injection and result analysis for IP, SoC, and system designs. The solution is built on the Incisive® verification platform and is available as part of the Cadence® System Development Suite.
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Requirements management flow
The requirements management flow solution is an adaptation of metric-driven verification (MDV) that targets industries with a mandate to track requirements thru verification completion. The requirements management flow starts from an in-house or third-party requirements management tool, and provides round-trip verification closure of top-level requirements in an automated MDV structure. It uses requirements and specifications to create verification plans capturing verification intent, performs metrics analysis and reporting, measures progress, and automates verification tasks. Most importantly, it provides traceability to the implementation of those requirements, as well as change management capabilities.
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TLM-driven design and verification methodology
Transaction-level modeling (TLM) raises the hardware abstraction to meet software performance requirements. It uses the coding of untimed and timed models to achieve 10x faster IP reuse, 2x faster verification turnaround, up to 50% shorter debug cycle, and much broader micro-architecture exploration. It is tightly integrated with simulation- and hardware-based engines to optimize tradeoffs—from systems to silicon—among latency/throughput, power consumption, and size.
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Low-power verification
Low-power verification adds planning and management integration to high-accuracy low-power simulation using standard power formats. It enables coherent low-power verification from systems to silicon by generating verification plans and assertions from the power format and by integrating with UVM IP/subsystem tests. Simulation accuracy is achieved with advanced engine techniques that model silicon implementation details in RTL for high-performance low-power simulation and debug.
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Digital-centric mixed-signal (DMS) verification
DMS verification targets high-performance mixed-signal SoC and IP verification by using real number models (RNMs) in Verilog-AMS and SystemVerilog (SV). It allows customers to model different parts of their designs at different levels of abstraction, from accurate behavioral models down to transistor levels, enabling full mixed-signal SoC verification using digital solvers only. IP/subsystem and SoC verification now require more accuracy than digital Verilog/VHDL alone can offer. SV-real/wreal models are being used more often to discretely model the analog portions of the design as the handoff between analog and digital designers and are easily portable between Virtuoso and Incisive environments. Due to its digital-centric use model, it targets high-volume, digital-centric nightly regressions. This flow naturally integrates with planning and management using assertions and coverage, enabling coherent mixed-signal SoC verification. Operating with both SV and e, DMS enables UVM testbenches to verify mixed-language design in IP/subsystem regression.
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SoC Performance Verification
The Cadence Interconnect Workbench is designed to meet the needs of verification engineers and system architects by identifying bottlenecks before they are locked in silicon. Interconnect Workbench analyzes simulation results from multiple SoC interconnect configurations and graphically displays bandwidth and latency comparisons.
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Verification apps
Verification apps are well-documented tool capabilities or methodologies focused on specific high-value problems. These problems are solved more efficiently using assertions for automated checking along with formal-based methods and/or a combination of formal, simulation, and metric-driven techniques rather than simulation-based methods alone. Additionally, the barrier to creating properties and the need for assertion-based verification (ABV) expertise are significantly reduced through either automated property generation or pre-packaged properties (provided).
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Assertion-based verification
Assertion-based verification (ABV) allows teams to start verification earlier and remove bugs faster. It captures design intent, detects errors close to the source, provides coverage information, and enables formal analysis. ABV supports industry-standard languages and includes unique assertion-based verification IP to simplify adoption. Our new verification apps automate and/or provide packaged solutions to many common problems that are optimally solved using an ABV approach.
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Universal Verification Methodology (UVM)
The Universal Verification Methodology (UVM) is the Accellera Systems Initiative standard for IP/subsystem verification. It fosters the creation of reusable verification IP with a well-defined UVM verification component architecture that scales from block to system verification and across projects. Architected to support multiple languages, the UVM provides coherent verification across abstractions and across digital, analog, and low-power domains. It runs with both simulation- and hardware-based engines to generate data required by metric-driven verification (MDV) to enable comprehensive SoC planning and management.
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Training in Verification Science
The verification task is complex, but the science of verification can be demystified through training. Udacity training offers the latest material and provides in-depth training to foster expert-level knowledge. The Cadence interactive Learning Series (iLS) provides knowledge models that engineers can work through at their desk. Short video-based training is also available for a wide range of subjects on the Cadence YouTube channel. Engineers can also take traditional classroom-style training from the Cadence course catalog. Finally, all of this knowledge can be explored and applied in the Incisive Verification Kit.
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