Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Products
> Logic Design
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Company Location
*
Comments:
*
Send Yourself A Copy
Logic Design
Chip planning
Decisions made during the architectural phase of the IC design cycle have a major impact on the ultimate size, power consumption, performance, and cost of the final chip. Cadence
®
chip planning solutions enable design teams to balance these often conflicting goals by performing rapid what-if analysis and optimizing design specifications to achieve an optimal chip plan.
Cadence InCyte Chip Estimator
Enables accurate estimation of IC size, power consumption, leakage, performance achievability, and cost. Provides an architectural exploration environment where users can quantify and compare a vast number of chip implementation options to balance technical and economic goals.
Learn more
»
Cadence Chip Planning System
An enterprise-class IC planning and IP reuse environment designed for larger, global organizations needing the utmost in technical and economic estimation accuracy. Provides support for estimation with custom IP and manufacturing processes. Features a comprehensive IP reuse management system.
Learn more
»
Constraint design and validation
Timing constraints drive the optimization and measurement of a chip toward its most critical project goals, yet constraint design remains a mostly manual and error-prone process. Since timing constraints define the clocks, they are also fundamental to establishing clock domain crossings. Cadence® technology automates the validation of constraints and clock-domain crossings to improve design productivity and quality and to ensure that the silicon functions as intended.
Encounter Conformal Constraint Designer
Automates the validation and refinement of constraints to ensure that timing constraints are valid throughout the entire design process. Identifies issues with clock-domain crossings early in the design process, helping designers achieve convergence on design goals.
Learn more
»
Logic synthesis
Creating the best balance of performance, power, and area intent from a given RTL has become an increasingly complex task—especially given the many abstraction levels and implementation options coupled with uncertainties surrounding the effects of physical interconnect on design convergence. Cadence® global logic synthesis provides new algorithms and approaches to automate the critical tradeoff process involved in achieving multiple and sometimes conflicting goals to realize successful silicon.
Encounter RTL Compiler
Allows engineers to concurrently optimize timing, area, power, and signal integrity intent. Offers a unique set of patented global-focus algorithms and physically-aware layout estimation capability.
Learn more
»
Encounter RTL Compiler Advanced Physical Option
Enables logic designers to account for physical interconnect—without the need to learn how to do physical design
Learn more
»
Equivalence checking
Design teams must ensure their RTL functions according to specification, while also coping with the complex transformations that their RTL undergoes along the path to silicon. Equivalence checking employs formal methods to exhaustively verify that a transformed netlist is functionally equivalent to the “golden” RTL or netlist. Cadence® equivalence checking technology works completely independent of implementation algorithms, eliminating false positives and catching logic bugs that would otherwise make it into the implemented chip.
Encounter Conformal Equivalence Checker
Formal verification technology for fast and accurate bug detection and correction
Learn more
»
Low-power validation
Implementing aggressive power reduction techniques affects the functionality of a design, and it causes logic and structural transformations during implementation. Cadence® low-power validation technology delivers early validation of power intent specifications using the production-proven Common Power Format (CPF). It also ensures proper implementation of power-saving logic and structures throughout the design flow.
Encounter Conformal Low Power
Enables the creation and validation of power intent in context of the design. Combines low-power equivalence checking with structural and functional checks to enable full-chip verification of power-efficient designs.
Learn more
»
Engineering change order
Whether it’s adding or removing logic in a design or cleaning up routing for signal integrity, ECOs can be a risky and time-consuming manual process. Even if the change is implemented in the netlist, there might not be enough spare gates on the mask to physically implement the change. Cadence® technology combines automatic ECO analysis and design netlist modification with world-class equivalence checking, allowing designers to implement ECOs for pre- and post-mask layout. Capturing upfront intent of whether correct implementation is achievable, design teams can now change plans and target workable solutions to drive convergence and stay on schedule.
Encounter Conformal ECO Designer
Cadence ECO solutions combine automatic ECO analysis, logic optimization, and design netlist modification with world-class equivalence checking to provide superior performance, productivity, and predictability, helping you achieve convergence on your design goals.
Learn more
»
Encounter Test
Silicon verification and yield learning system
Silicon process-related phenomena combined with exploding SoC design complexity have introduced new transition-based defect types. As a result, engineers rely on more advanced—and often more expensive—at-speed or faster-than-at-speed test methodologies to ensure higher quality and profitability.
For successful SoC and analog/mixed-signal (AMS) design and test implementation, the need for predictability in both physical and test design flows is absolute. Integration of technologies that are conventionally standalone is essential for achieving concurrent optimization with meaningful correlation to downstream physical and test design flows.
Native to the Encounter RTL Compiler global synthesis environment, Encounter Test provides a unified platform that expands the definition of silicon quality to include area, timing, power, and testability. Encounter Test comprises three product technologies: Encounter DFT Architect, Encounter True-Time ATPG, and Encounter Diagnostics.
DFT Architect, combined with Encounter RTL Compiler, enables early and concurrent design-for-test (DFT) planning, testability, analysis, and verification. Links to Encounter True-Time ATPG achieves downstream correlation for greater predictability, the highest quality netlist, and fewer iterations for physical and test design flows. Encounter Diagnostics, with links to True-Time ATPG, provides the most accurate diagnostics solution available on the market for silicon bring-up, debug, and yield optimization. It delivers a comprehensive volume and precision diagnostics flow that ensures efficiency in yield learning and productivity in precision failure analysis.
Our Encounter Front-End Test Design and Diagnostics development teams have prioritized technology goals to include test quality, cost, and power—all facilitated through product integration—which boosts ease-of-use, productivity, predictability, and ultimately profit.
Encounter DFT Architect
With its synthesis-based, unified methodology for creating full-chip power-aware tests, Encounter DFT Architect addresses and optimizes multiple design and manufacturing objectives—such as timing, area, wiring, and power—for today’s complex ICs and SoCs.
Learn more
»
Encounter True-Time ATPG
Delivers the industry’s most comprehensive automated test pattern generation (ATPG) solution. Through a broad array of pre-defined and user-defined static and transition-based faults, multiple on-chip compression architectures, and power-aware test capabilities, Encounter True-Time ATPG achieves the most stringent quality and cost goals.
Learn more
»
Encounter Diagnostics
The industry’s most advanced solution for accelerating yield ramp and reducing costs in manufacturing environments. It rapidly analyzes thousands of failures, identifies the source of systematic yield loss, and pinpoints defect location in the netlist and layout.
Learn more
»
Static timing analysis
Performing static timing analysis on today’s chips—where physical interconnect dominates the delay equation—requires a way for logic designers to account for physical effects without having to learn physical design. Cadence
®
static timing analysis increases productivity and accuracy by incorporating this data in a powerful logic-design–oriented use model and analysis environment.
Encounter Timing System
Offers silicon-accurate timing signoff and signal integrity analysis that ensures operational chips after tapeout.
Learn more
»
Formal analysis
Cutting design and verification time while improving product quality requires a formal means of verifying RTL functional correctness with assertions that bypasses the need for testbench simulation. Cadence
®
formal analysis technology puts design teams months ahead of testbench simulation by supporting an assertion-based methodology and delivering fast and predictable RTL block bring-up without test vectors.
Incisive Formal Verifier
Performs formal analysis in the assertion-based verification and debug of RTL block designs, before testbench availability, to speed design convergence.
Learn more
»
Testbench simulation
Verification often creates a bottleneck in delivering today's highly integrated electronic systems and chips. Cadence
®
testbench simulation solutions simplify and speed verification—from individual blocks to the full chip and all the way to the project level—by combining leading-edge process automation with the comprehensive Plan-to-Closure Methodology.
Cadence Low-Power Methodology Kit
Delivers the most accurate volume and precision diagnostics capability available on the market. Accelerates silicon bring-up and optimizes yield ramp with device and fault modeling.
Learn more
»
Design and verification IP modeling
To maximize design predictability and quality, engineers need reusable verification IP that spans block to chip to system levels and derivative projects. Cadence
®
Verification IP (VIP) automates and speeds compliance verification for advanced communication protocols, provides metric-based data to interpret and report simulation results, and supports all IEEE-standard languages.
Incisive Verification IP
Supports advanced testbenches, transaction-based acceleration for high-level testbenches, assertion-based VIP for formal, simulated, and accelerated block-level verification, and emulation and in-circuit verification.
Learn more
»
Verification management
Achieving a predictable path to verification closure requires automated planning and metrics management with comprehensive coverage at block, chip, and system levels. Cadence
®
technology tracks the progress of an evolving design against its functional, performance, and schedule objectives simultaneously. It automates the deployment of simulation runs, analyzes failures and coverage data, and guides the steps toward closure.
Incisive Design Team Manager
Drives verification closure using incrementally developed assertion and test list plans. Captures and quickly prioritizes failures.
Learn more
»
Cadence Low-Power Methodology Kit
Delivers the most accurate volume and precision diagnostics capability available on the market. Accelerates silicon bring-up and optimizes yield ramp with device and fault modeling.
Learn more
»
Incisive Desktop Manager
Automates and guides the everyday deployment and visualization of verification tasks and results.
Learn more
»
Incisive Verification IP
Supports advanced testbenches, transaction-based acceleration for high-level testbenches, assertion-based VIP for formal, simulated, and accelerated block-level verification, and emulation and in-circuit verification.
Learn more
»
Cadence Chip Planning System
An enterprise-class IC planning and IP reuse environment designed for larger, global organizations needing the utmost in technical and economic estimation accuracy. Provides support for estimation with custom IP and manufacturing processes. Features a comprehensive IP reuse management system.
Learn more
»
Cadence InCyte Chip Estimator
Enables accurate estimation of IC size, power consumption, leakage, performance achievability, and cost. Provides an architectural exploration environment where users can quantify and compare a vast number of chip implementation options to balance technical and economic goals.
Learn more
»
Cadence Low-Power Methodology Kit
Delivers the most accurate volume and precision diagnostics capability available on the market. Accelerates silicon bring-up and optimizes yield ramp with device and fault modeling.
Learn more
»
Encounter Conformal Constraint Designer
Automates the validation and refinement of constraints to ensure that timing constraints are valid throughout the entire design process. Identifies issues with clock-domain crossings early in the design process, helping designers achieve convergence on design goals.
Learn more
»
Encounter Conformal ECO Designer
Cadence ECO solutions combine automatic ECO analysis, logic optimization, and design netlist modification with world-class equivalence checking to provide superior performance, productivity, and predictability, helping you achieve convergence on your design goals.
Learn more
»
Encounter Conformal Equivalence Checker
Formal verification technology for fast and accurate bug detection and correction
Learn more
»
Encounter Conformal Low Power
Enables the creation and validation of power intent in context of the design. Combines low-power equivalence checking with structural and functional checks to enable full-chip verification of power-efficient designs.
Learn more
»
Encounter DFT Architect
With its synthesis-based, unified methodology for creating full-chip power-aware tests, Encounter DFT Architect addresses and optimizes multiple design and manufacturing objectives—such as timing, area, wiring, and power—for today’s complex ICs and SoCs.
Learn more
»
Encounter Diagnostics
The industry’s most advanced solution for accelerating yield ramp and reducing costs in manufacturing environments. It rapidly analyzes thousands of failures, identifies the source of systematic yield loss, and pinpoints defect location in the netlist and layout.
Learn more
»
Encounter RTL Compiler
Allows engineers to concurrently optimize timing, area, power, and signal integrity intent. Offers a unique set of patented global-focus algorithms and physically-aware layout estimation capability.
Learn more
»
Encounter RTL Compiler Advanced Physical Option
Enables logic designers to account for physical interconnect—without the need to learn how to do physical design
Learn more
»
Encounter Timing System
Offers silicon-accurate timing signoff and signal integrity analysis that ensures operational chips after tapeout.
Learn more
»
Encounter True-Time ATPG
Delivers the industry’s most comprehensive automated test pattern generation (ATPG) solution. Through a broad array of pre-defined and user-defined static and transition-based faults, multiple on-chip compression architectures, and power-aware test capabilities, Encounter True-Time ATPG achieves the most stringent quality and cost goals.
Learn more
»
Incisive Design Team Manager
Drives verification closure using incrementally developed assertion and test list plans. Captures and quickly prioritizes failures.
Learn more
»
Incisive Desktop Manager
Automates and guides the everyday deployment and visualization of verification tasks and results.
Learn more
»
Incisive Formal Verifier
Performs formal analysis in the assertion-based verification and debug of RTL block designs, before testbench availability, to speed design convergence.
Learn more
»
Incisive Verification IP
Supports advanced testbenches, transaction-based acceleration for high-level testbenches, assertion-based VIP for formal, simulated, and accelerated block-level verification, and emulation and in-circuit verification.
Learn more
»
Content Query Web Part [1]
Cadence Drives Giga-Gate/Gigahertz Design at 28nm with New Digital End-to End Flow
Cadence Offers Optimized Implementation Methodology for Silicon Realization of New ARM Cortex-A15 MPCore Processor
New White Paper: 3D ICs With TSVs — Design Challenges and Requirements
speakTECH Feeder Viewer for Community Server
Recent Blog Posts
Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose
Tips for Fixing Timing Violations and Adopting Best Practices for Optimization with RTL Compiler
Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)
Visit the Community
»
Content Query Web Part [2]
Cadence Services
Support & Training
Software Downloads
TSMC Libraries
Hosted Design Solutions