Incorporating advanced power management techniques
Power consumption in wireless consumer devices has become a key part of many product specifications. Even for wired devices, in which battery power has not traditionally been an issue, considerations of packaging, reliability, and cooling costs bring power to the forefront. As designs migrate to sub-90nm process nodes, power management becomes a serious concern across the entire design and manufacturing chain.
To achieve required power targets, design teams must adopt advanced power management techniques such as multi-supply multi-voltage (MSMV), dynamic voltage and frequency scaling (DVFS), and power shutoff (PSO). Such techniques, however, increase design complexity and introduce risk.
Conventional design flows fail to address the additional considerations for incorporating advanced low-power design techniques. Consequently, design teams often resort to ad hoc or inflexible methodologies that result in lower productivity, increased risk of silicon failure, longer time to market, and inferior product performance.
An integrated solution for design, verification, and implementation of low-power SoCs
To help design teams adopt advanced power management techniques, Cadence has developed the industry’s first complete solution for the design, verification, and implementation of low-power chips. The Cadence® Low-Power Solution combines a variety of Cadence technologies that leverage the Si2 Common Power Format (CPF)—which specifies power-saving techniques early in the design process—enabling design teams to share and reuse low-power intelligence.
The Cadence Low-Power Solution:
- Reduces risk: By minimizing the need for manual intervention and using a robust verification methodology, design teams can eliminate silicon failure risks that stem from functional and structural flaws.
- Boosts productivity and speeds time to market With integrated logic design, verification, and implementation technologies, design teams maintain high productivity levels. By reducing the number of iterations within the flow and limiting silicon re-spins, design teams can predictably address time-to-market concerns.
- Increases quality of silicon: Through easy-to-use "what-if" exploration early in the flow, designers can identify optimal power architectures to achieve desired specifications. Subsequently, optimization engines in the implementation flow help achieve superior tradeoff among timing, power, and area targets.