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System Design and Verification
System simulation and analysis
To ensure correct system functionality, design and verification teams must simulate, debug, verify, and analyze system hardware and software in-parallel under all expected and unexpected conditions—pre-silicon. Using Cadence
®
system simulation and analysis, engineers can perform thorough plan- and metrics-driven hardware/software co-verification at the transaction level using mixed HDLs together with SystemC
®
.
With the most comprehensive support for the latest industry standards—OSCI
®
TLM 1.0/2.0 (transaction-level modeling), IEEE 1850 PSL (assertion-based verification), and SCE-MI 2.0 (transaction-based acceleration)—engineers can apply the full breadth of Incisive
®
verification capabilities to SystemC and mixed-HDL designs across both hardware-based and software-based simulation environments. Advanced SystemC simulation features including save/restore, transaction-level recording, and multi-language hierarchical visualization/analysis to maximize engineering productivity for hardware-software debugging, verification, and validation.
Incisive Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Incisive Palladium Dynamic Power Analysis
Extends the Cadence Palladium® III accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation with Palladium III to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Incisive Enterprise Simulator
Performs multi-language coverage-driven functional verification, analysis, and debug from system level to gate level. Automates testbench generation.
Learn more
»
Incisive Software Extensions
Provides the productivity, predictability, and quality benefits of metric-driven techniques for hardware/software co-verification, unified hardware/software debugging, and embedded software tracing technology. Leverages and extends existing Incisive verification environment for software running on any processor.
Learn more
»
Incisive Xtreme series
Offers the ease-of-use, precision, control, and visibility of an Incisive simulator. Provides built-in acceleration and emulation capabilities through instant hot-swap between simulation and acceleration. Enables simulation acceleration and emulation of sub-systems and SoCs.
Learn more
»
High-level synthesis
To achieve a 10-fold leap in productivity, system design and verification engineers must begin designing at a higher level of abstraction. Using Cadence
®
high-level synthesis, teams automatically generate high-quality RTL code for their application with as little as 10% of the manual effort.
C-to-Silicon Compiler
Next-generation high-level synthesis technology automatically generates synthesizable Verilog RTL from timed or untimed C/C++/SystemC. Delivers the highest code quality in terms of area and performance.
Learn more
»
Simulation acceleration
To reduce simulation time, system design and verification teams need to use a hardware-assisted verification system while reusing their established behavioral testbench and verification environment. Cadence
®
high-performance, high-capacity simulation acceleration technology increases performance over RTL simulation with direct or standard interfaces to a variety of testbench languages and a highly productive simulator-like environment.
Incisive Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Incisive Palladium Dynamic Power Analysis
Extends the Cadence Palladium® III accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation with Palladium III to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Incisive Software Extensions
Provides the productivity, predictability, and quality benefits of metric-driven techniques for hardware/software co-verification, unified hardware/software debugging, and embedded software tracing technology. Leverages and extends existing Incisive verification environment for software running on any processor.
Learn more
»
Incisive Xtreme series
Offers the ease-of-use, precision, control, and visibility of an Incisive simulator. Provides built-in acceleration and emulation capabilities through instant hot-swap between simulation and acceleration. Enables simulation acceleration and emulation of sub-systems and SoCs.
Learn more
»
Emulation
To undertake comprehensive system-level verification, engineers must stress and validate their design in a scalable verification environment—one that offers a high degree of control and visibility, applies system-level stimulus to the design, and verifies the performance and behavior of the integrated system. Using Cadence
®
high-throughput emulation technology, design and verification teams can rapidly bring-up, verify, debug, and turnaround their hardware and software designs using realistic system-level environments.
Incisive Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Incisive Palladium Dynamic Power Analysis
Extends the Cadence Palladium® III accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation with Palladium III to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Cadence SpeedBridge Adapters
Enable a full-speed device to interface directly with a design running at emulation speed. Support in-circuit emulation under real-world operating conditions. Reduce risk by enabling the emulator to leverage stimuli and responses from external sources that ensure the design’s correct in-system behavior.
Learn more
»
Incisive Xtreme series
Offers the ease-of-use, precision, control, and visibility of an Incisive simulator. Provides built-in acceleration and emulation capabilities through instant hot-swap between simulation and acceleration. Enables simulation acceleration and emulation of sub-systems and SoCs.
Learn more
»
Hardware/software co-verification
For effective system-level verification, engineers require a high-performance environment that allows access to hardware and software debuggers while running various system-level scenarios using firmware, drivers, operating systems, and application software. Conventional simulation of designs at RTL with embedded software at the system level is impractical and has performance limitations. Offering higher throughput, superior hardware/software debug, and fast compilation, Cadence
®
hardware/software co-verification technology allows software developers to run and debug their designs on top of a hardware-assisted verification platform.
Incisive Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Incisive Palladium Dynamic Power Analysis
Extends the Cadence Palladium® III accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation with Palladium III to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Incisive Software Extensions
Provides the productivity, predictability, and quality benefits of metric-driven techniques for hardware/software co-verification, unified hardware/software debugging, and embedded software tracing technology. Leverages and extends existing Incisive verification environment for software running on any processor.
Learn more
»
Incisive Xtreme series
Offers the ease-of-use, precision, control, and visibility of an Incisive simulator. Provides built-in acceleration and emulation capabilities through instant hot-swap between simulation and acceleration. Enables simulation acceleration and emulation of sub-systems and SoCs.
Learn more
»
Verification IP integration
To ensure correct system verification, engineers must drive stimulus matching the specific protocols interfacing with their designs and check the design response. They must also test the interface protocols under real-world operating conditions. Integrating Cadence® verification IP, engineers can rapidly construct a complete system verification environment for both acceleration and emulation.
System-level verification IP
Learn more
»
Memory models for emulation
Learn more
»
Cadence SpeedBridge Adapters
Enable a full-speed device to interface directly with a design running at emulation speed. Support in-circuit emulation under real-world operating conditions. Reduce risk by enabling the emulator to leverage stimuli and responses from external sources that ensure the design’s correct in-system behavior.
Learn more
»
Incisive Verification IP
Supports advanced testbenches, transaction-based acceleration for high-level testbenches, assertion-based VIP for formal, simulated, and accelerated block-level verification, and emulation and in-circuit verification. Available for a wide range of complex protocols (PCI Express, AMBA, USB, OCP, Ethernet, and more). OVM-compliant and supports a variety of IEEE-standard languages.
Learn more
»
Assertion-based verification
To boost verification productivity and enhance debug visibility, system design and verification teams require an assertion-based verification environment that unifies software, languages, IP, debug, and coverage. Cadence
®
assertion-based verification enables the detection of bugs close to the source during various design phases. Cadence technologies for simulation, acceleration, emulation, verification planning and management, comprehensive coverage, and formal verification enable assertion-based verification.
The Open Verification Library (OVL) and the Incisive Assertion Library are supported along with SVA and PSL languages in various Cadence Incisive
®
verification technologies. SVA and PSL can represent very complex temporal conditions in a concise manner and they work seamlessly in simulation, acceleration, and emulation. With broad support for industry-standard languages and libraries, Cadence assertion-based verification technologies help teams achieve verification completeness and measure it against comprehensive coverage. Assertions can also serve the purpose of documentation, which is helpful when reusing IP from one project to another.
Synthesizable testbenches and in-circuit emulation using
SpeedBridge
®
Adapters
are common use modes when Incisive Palladium and Xtreme accelerators and emulators can be used. These use modes allow customers to run long system-level tests with high performance. Assertions are very useful during these long tests because they constantly monitor the design behavior, thus increasing debug productivity and the predictability of the design state.
Incisive Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Incisive Palladium Dynamic Power Analysis
Extends the Cadence Palladium® III accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation with Palladium III to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Incisive Enterprise Manager
Automates and guides verification from planning to closure. Includes SystemVerilog and e functional coverage capabilities.
Learn more
»
Incisive Xtreme series
Offers the ease-of-use, precision, control, and visibility of an Incisive simulator. Provides built-in acceleration and emulation capabilities through instant hot-swap between simulation and acceleration. Enables simulation acceleration and emulation of sub-systems and SoCs.
Learn more
»
Metric-driven verification
To efficiently and accurately guide projects from initial planning to verification closure, engineers need automated verification management solutions that utilize metrics. Cadence
®
metric-driven technologies automate time-consuming manual verification tasks at block, chip, system, and project levels. Using a metric-driven approach, system designers and verification teams can streamline the verification process and better analyze both failures and coverage to debug their designs.
Incisive Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Incisive Palladium Dynamic Power Analysis
Extends the Cadence Palladium® III accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation with Palladium III to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Incisive Enterprise Manager
Automates and guides verification from planning to closure. Includes SystemVerilog and e functional coverage capabilities.
Learn more
»
Incisive Xtreme series
Offers the ease-of-use, precision, control, and visibility of an Incisive simulator. Provides built-in acceleration and emulation capabilities through instant hot-swap between simulation and acceleration. Enables simulation acceleration and emulation of sub-systems and SoCs.
Learn more
»
Low-power verification and analysis
To verify that complex system-level designs are optimized for low power, engineers need an automated process for identifying bugs and ensuring that all power-related logic is exercised. Cadence
®
low-power verification and analysis technology delivers the industry's first complete flow that integrates logic design, verification, and implementation technologies with the Common Power Format (CPF). During the system verification process, engineers can use the flow with Cadence emulation technology to further enhance productivity and predictability.
Incisive Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Incisive Palladium Dynamic Power Analysis
Extends the Cadence Palladium® III accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation with Palladium III to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Incisive Enterprise Simulator
Performs multi-language coverage-driven functional verification, analysis, and debug from system level to gate level. Automates testbench generation.
Learn more
»
Cadence Low-Power Methodology Kit
Streamlines the adoption of low-power techniques and optimizes their usage. Eliminates risk with a complete front-to-back methodology, best practices, checklists, and reference flows.
Learn more
»
Cadence Low-Power Methodology Kit
Streamlines the adoption of low-power techniques and optimizes their usage. Eliminates risk with a complete front-to-back methodology, best practices, checklists, and reference flows.
Learn more
»
Cadence SpeedBridge Adapters
Enable a full-speed device to interface directly with a design running at emulation speed. Support in-circuit emulation under real-world operating conditions. Reduce risk by enabling the emulator to leverage stimuli and responses from external sources that ensure the design’s correct in-system behavior.
Learn more
»
C-to-Silicon Compiler
Next-generation high-level synthesis technology automatically generates synthesizable Verilog RTL from timed or untimed C/C++/SystemC. Delivers the highest code quality in terms of area and performance.
Learn more
»
Incisive Enterprise Manager
Automates and guides verification from planning to closure. Includes SystemVerilog and e functional coverage capabilities.
Learn more
»
Incisive Enterprise Simulator
Performs multi-language coverage-driven functional verification, analysis, and debug from system level to gate level. Automates testbench generation.
Learn more
»
Incisive Palladium Dynamic Power Analysis
Extends the Cadence Palladium® III accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation with Palladium III to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Incisive Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Incisive Software Extensions
Provides the productivity, predictability, and quality benefits of metric-driven techniques for hardware/software co-verification, unified hardware/software debugging, and embedded software tracing technology. Leverages and extends existing Incisive verification environment for software running on any processor.
Learn more
»
Incisive Verification IP
Supports advanced testbenches, transaction-based acceleration for high-level testbenches, assertion-based VIP for formal, simulated, and accelerated block-level verification, and emulation and in-circuit verification. Available for a wide range of complex protocols (PCI Express, AMBA, USB, OCP, Ethernet, and more). OVM-compliant and supports a variety of IEEE-standard languages.
Learn more
»
Incisive Xtreme series
Offers the ease-of-use, precision, control, and visibility of an Incisive simulator. Provides built-in acceleration and emulation capabilities through instant hot-swap between simulation and acceleration. Enables simulation acceleration and emulation of sub-systems and SoCs.
Learn more
»
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System-Level Low-Power Webinar: Reduce System-Level Low-Power Requirements from Start to Finish
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