Cadence DFM Services Datasheet
As technology advances to 40nm and beyond, designs are being scaled down to meet the ever-increasing demand for more functionality contained in a single chip. Hotspot detection is more important than ever and requires new practices beyond traditional rule-based checks.
Cadence and TSMC collaborate to deliver best-in-class design-for-manufacturing (DFM) services, which include model-based simulation of LPC and CMP verification for designs at 40nm down to 28nm. The goal is to help design teams effectively detect litho or CMP hotspots and fix them during the IC design phase, prior to tapeout.
Litho process check (LPC)
LPC predicts the silicon image of the design shapes and detects where the fidelity between silicon and design intent is problematic, or where printability induces too much variability. Using proprietary models provided by TSMC via encrypted DFM Design Kits (DDKs), critical hotspots are detected and this information is given to designers for fixing before committing to manufacturing.
Chemical mechanical polishing (CMP) check
CMP checks take into account multi-level and long-range effects. CMP hotspots are shown as a density heat map. This helps designers understand the root cause of the CMP issue, which can be insufficient metal fill implementation or too much variation between high- and low-density areas of the block or chip.
Flexibility to choose
Cadence DFM Services provide IC designers with additional flexibility beyond purchasing qualified DFM tools to fulfill their DFM needs.
A DFM service model is available for design teams that desire zero knowledge-ramp time, minimal tool learning, and no IT burden. This is where Cadence DFM Services aims to deliver the best cost of ownership and technical expertise by collaborating with TSMC. The Cadence DFM Services team uses TSMC-qualified tools: Cadence Litho Physical Analyzer (LPA) for LPC and Cadence CMP Predictor for industry-leading CMP analysis.
The Cadence DFM Services infrastructure uses the latest TSMC DDKs for 40-28nm nodes to ensure accuracy. It leverages the cloud infrastructure and the compute power of hundreds of central processing units (CPUs) assembled to provide timely completion of full-chip LPC or CMP checks on all required layers, delivering the fastest turnaround time. The hardware infrastructure can easily scale to support advanced-node design needs—whether it’s supporting a few early pipe-cleaner jobs or multiple large designs concurrently. A state-of-the-art IT and security infrastructure further ensure that the customer’s design data is secure and protected from unauthorized access.
- Best total cost of ownership: eliminates having to invest in software tools or learn new tools, and uses a multi-CPU infrastructure
- Efficient access: provides priority turnkey access to TSMC-qualified LPC and CMP analysis tools
- Reduced schedule risk: allows customers to verify block-level LPC and CMP compliance early with a “pipe cleaner”
- Optimal time to results: harnesses hundreds of dedicated CPUs run in our server farm for fast turnaround time
- Security: leverages a highly reliable and state-of-the-art IT and security infrastructure, which ensures protection from unauthorized access
- Cadence and TSMC expertise: leverages many years of experience through long-term DFM collaboration between Cadence and TSMC
- Low-risk learning experience: provides a learning experience for designers to understand DFM while designing with advanced process nodes
- Enabling repair: output report enables automated fixing in digital and custom implementation flows
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