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 3D-IC Solution 

  • Overview
  • Design IP
  • Implementation
  • Analysis and Verification
  • IC/Package Co-Design
  • Test
 
Test Test raises many challenges for 3D-ICs, including access to die inside a stack and proper handling of thinned wafers. New standards and tool support are both required to validate that design intent is maintained once 3D-IC silicon is realized, and to diagnose issues properly if the system doesn’t behave as intended.

3D-IC test must be considered at three levels: wafer or pre-bond test (known-good die prior to stacking), mid-bond/post-bond test (to ensure all TSV-based connections are realized during manufacturing), and post-packaging test (after 3D-IC assembly into the package).

Cadence provides a comprehensive methodology for 3D-IC design for test (DFT) and automatic test pattern generation (ATPG) that includes:
  • DFT architecture that controls and observes individual die from the chip I/Os, while also providing different test access modes (such as a mode for a known-good die test or a known-good stack test)
  • Mapping of TSV defects to known fault types
  • Other test technologies like embedded pattern compression, boundary scan, core and 3D wrapping, memory built-in self-test (MBIST), logic built-in self-test (LBIST), reduced pin count testing, and on-chip clocking for at-speed testing
Benefits
  • Allows Heterogeneous integration of different dies
  • Improved performance
  • Reduced power consumption
  • Maximum functionality in a smaller form factor to support numerous applications in networking, graphics, mobile communications and networking
Products
IC/Package Co-Design For an optimal, cost-effective, and fully optimized 3D-IC stack, it is essential that chip, package, and board are considered holistically and designed in tandem. An optimized IC stack may be very costly if it ultimately is going to sit on an expensive package—so, some system planning must be done before IC implementation.

The Cadence 3D-IC solution incorporates:
  • I/O feasibility planning between chip, package, and board
  • Connectivity management
  • 3D visualization
Benefits
  • Allows Heterogeneous integration of different dies
  • Improved performance
  • Reduced power consumption
  • Maximum functionality in a smaller form factor to support numerous applications in networking, graphics, mobile communications and networking
Products
Chip-Level Analysis and Verification Extraction and analysis tools are crucial for design convergence. However, existing extraction and analysis tools need to be extended for 3D-ICs. For example, the tools must consider RLC parasitics for TSVs, micro-bumps, and interposer routing. Analysis tools must be 3D-aware. Timing, signal integrity, power, and thermal gradients must be analyzed across multiple die. And multi-die static timing must be validated with an understanding of the interactions between multiple die and with the package.

Cadence chip-level analysis and verification technology consists of 3D extensions to Encounter Timing System, Encounter Power System, QRC Extraction, and Physical Verification System. These tools provide robust capabilities for stack analysis and verification.
Benefits
  • Allows Heterogeneous integration of different dies
  • Improved performance
  • Reduced power consumption
  • Maximum functionality in a smaller form factor to support numerous applications in networking, graphics, mobile communications and networking
Products
Implementation 3D-IC is about heterogeneous integration, combining digital and custom dies in same stack. Whether it’s 2.5D or 3D, it is essential that a 3D-IC solution enables 3D implementation and handoff between custom and digital fabrics seamlessly.

Synthesis, floorplanning, placement, and routing of these 3D/2.5D ICs brings new considerations and challenges to both custom and digital domains. For example, there are new layout rules that may be driven by features on adjacent die. The back-side redistribution layer (RDL) is a new layout layer. And given their size, TSVs themselves are a significant new layout feature.

TSVs are very large compared to logic gates and other circuit features. Thus, the number and location of TSVs is crucial. With too many TSVs, the wire length goes up. TSVs also cause coupling, which can be reduced by adding space to their keep-out zones, but this adds to the area.

Digital Implementation Encounter Digital Implementation System and Encounter RTL Compiler provide a comprehensive “double-side--aware” methodology, which includes:
  • A TSV-aware 3D floorplanning capability with unique abstraction technology to capture all the die and provide a unified representation of intent for placement and routing tools
  • Optimization of blocks, TSVs, and micro-bumps to improve performance and power
  • Multi-chip visualization with background views
  • Connectivity extraction, and timing and power analysis, maintained through TSV connections
Custom Implementation The Virtuoso custom IC design environment provides a comprehensive set of 2.5D/3D-IC technologies that include support for:
  • 3D-IC TSV/back-side connectivity
  • Adjacent die checking and debugging (inter-die shorts/opens and inter-die misalignments)
  • Route to micro-bumps and TSV
  • Bump file transfer support
  • Multi-die visualization with background views
Enabling both the custom and digital environments for implementation and sharing of data between the stacks is the key to optimizing the entire system.
Benefits
  • Allows Heterogeneous integration of different dies
  • Improved performance
  • Reduced power consumption
  • Maximum functionality in a smaller form factor to support numerous applications in networking, graphics, mobile communications and networking
Products
Design IP Wide I/O is a significant new direction for 3D-ICs, enabling faster memory access in the stacked scenario. Wide I/O memory is a new DRAM technology and an emerging JEDEC standard that calls for a 512-bit wide interface and 12.8GB per second bandwidth. In addition to high bandwidth, it promises low power consumption. It will initially target the mobile consumer marketplace, where space is at a premium, performance and power demands are stringent, and there is already a movement toward 3D-ICs.

The Cadence Wide I/O offering includes a configurable memory controller, physical layer (PHY), and verification IP (VIP). It goes beyond the proposed JEDEC specification by including such features as traffic reordering, which provides an optimal data flow with the best possible balance of bandwidth and latency. Additionally, Cadence modified its built-in self-test (BIST) capability to include new classes of errors that may result from 3D die stacking. Our Wide I/O memory controller was introduced in March 2011 and has been used in several test chips.

Wide I/O presents a compelling new technology for a new generation of mobile, high-bandwidth, low-power devices. The emerging JEDEC specification will help drive this technology and bring 3D-ICs with TSVs into the mainstream.
Benefits
  • Allows Heterogeneous integration of different dies
  • Improved performance
  • Reduced power consumption
  • Maximum functionality in a smaller form factor to support numerous applications in networking, graphics, mobile communications and networking
Products
Overview Consumer demand for increased bandwidth and low power in smaller form factor has forced design teams to pursue design and manufacturing alternatives to single system-on-chip (SoC) approaches. Moving to advanced geometries like 20nm/14nm is a natural progression; however, it has its own cost, yield, manufacturing, and IP reuse challenges. This has given way to a viable alternative of exploring the third dimension in design and manufacturing: 3D-ICs with through-silicon vias (TSVs).

3D-ICs with TSVs bring enormous possibilities to how a system can be built:
  • Heterogeneous integration
  • Improved performance
  • Reduced power consumption
  • Maximum functionality in a smaller form factor to support numerous applications in networking, graphics, mobile communications and networking.
Even though 3D-IC technology has had challenges such as lacking standards and supply chain, the good news is that 3D-IC enablement is evolving. Cadence has been working closely with customers and ecosystem partners for the last six years to develop a methodology for 3D-IC starting from planning to implementation, test, analysis, verification, and ultimately signoff.

Our 3D-IC solution is validated and tested on several customer designs, and includes:
  • 3D implementation (placement, optimization, routing) for custom and digital
  • 3D verification and analysis
  • Design for test (DFT)
  • IC/package co-design and system analysis
  • Required 3D-IC IP such as Wide I/O controller and PHY
  • System-level exploration
Benefits
  • Allows Heterogeneous integration of different dies
  • Improved performance
  • Reduced power consumption
  • Maximum functionality in a smaller form factor to support numerous applications in networking, graphics, mobile communications and networking
Products