It’s a mixed-signal world
The trend in mixed-signal design is rapidly evolving beyond traditional analog/mixed-signal (AMS) to large mixed-signal system-on-chip (SoC) designs that are the heart of today’s advanced devices. Cadence® Virtuoso® custom design technology continues to lead the industry in AMS design automation, but as customers are developing ever-larger mixed-signal SoC designs, there is a growing need for higher levels of automation to implement the vast amounts of digital control and processing logic.
AMS designs include more digital logic than ever before, and SoC designs now include more and more analog components. Having a solid, proven technology foundation in both digital and analog design is a pre-requisite for a viable solution, but the rigors of developing an advanced, mixed-signal SoC design demands much more. Just as timing, die size, and power must be considered in concert, analog and digital design interdependency is expanding at a rapid rate. Nearly every electronics product today is a multi-function product, requiring mind-boggling processing power to crunch data from antennas, filters, sensors, and interface cables. This fusion of digital processing and analog components is revealing the weaknesses of older design methodologies.
Advanced chip design has raised the ante at every process node, the price for which goes far beyond mask costs. New challenges include implementing complex analog/digital interactions, compensating for process variation, managing ever-more complex design rules, and handling extremely large designs efficiently. The conventional “divide-and-conquer” approach to AMS design no longer works for today’s more complex designs. At 65nm and below, more than 50 percent of design re-spins result from mixed-signal–related design errors. Mask re-spin costs can be in the millions of dollars, but this cost can be minuscule when compared to the cost of missing a market window.
It’s a mixed-signal world. Design teams need an efficient mixed-signal solution that tackles these design creation challenges, mitigates risks, and enables a timely, successful market launch.
An integrated solution for planning, design, verification, and implementation
The Cadence Mixed-Signal Solution encompasses technologies from all Cadence design environments —Virtuoso custom, Encounter® digital, Incisive® verification, and Allegro® system interconnect. It provides a complete methodology for planning-to-signoff that begins with early design planning and includes system and front-end design, functional verification, through to physical implementation. Unique to the Cadence Mixed-Signal Solution is its capabilities related to SoC and system-in-package (SiP) integration and verification across domains. It ensures that consistency and convergence are achieved. This comprehensive flow includes a flexible approach to methodology that adapts to the background, training, and preferences of the individual designer and the entire design team.
The Cadence Mixed-Signal Solution is based upon the only comprehensively proven solution for analog and custom design coupled with digital flows through the OpenAccess (OA) database, which ensures consistency between the analog and digital domains. The verification methodology spans IP block verification, model generation, and SoC verification using the Open Verification methodology (OVM). This fully integrated, highly automated mixed-signal solution is backed by industry-leading services capabilities and the industry's largest mixed-signal–focused industry alliance program.
The Cadence Mixed-Signal Solution
- Reduces risk: Through robust methodologies for verification model generation and validation that enables mixed-signal verification using a metrics-driven verification methodology.
- Boosts productivity and speeds time to market: Through a design methodology that leverages OA to provide seamless interoperability between the custom and digital domains. With integrated estimation, design, verification, implementation automation, and signoff technologies, design teams maintain high productivity levels. By reducing the number of iterations within the flow and limiting silicon re-spins, design teams can address time-to-market requirements with a high level of predictability.
- Increases quality of silicon: Through easy-to-use "what-if" exploration early in the design flow, designers can identify optimal architectures to achieve desired specifications. Throughout the implementation flow, best-in-class multi-objective optimization engines help designers achieve superior tradeoff among timing, power, and area targets. The solution also reduces over-design and eliminates excessive guard-banding.
- Increases predictability: By integrating implementation technologies earlier into the design flow, the solution shows designers what the outcome will look like early on. A comprehensive approach to design progress metrics ensures a steady, convergent path to closure from both functional and physical standpoints.
Key features
- Environment/Editors – The solution leverages industry-standard, best-in-class design, verification, and implementation environments and editors
- Engines – At the heart of the solutions is best-in-class, foundational analysis and design automation technology
- Methodology choices – To accommodate the unique needs of each product design, and to reflect the needs, training backgrounds, and preferences of each design team, the solution supports a full array of methodologies
- Languages – Central to its philosophy of choice, the solution supports mixed design languages
- Metric-driven design – Committed to using best practices in chip design program management, the solution uses a metric-driven approach to measure progress
Resources